EPC1PC8N vs EPC1PC8CC Comparaison
Comparaison détaillée côte à côte de EPC1PC8N par Intel et EPC1PC8CC par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC1PC8N | EPC1PC8CC |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $4,40 | $9,95 |
| Type de mémoire | OTP (One-Time Programmable) Configuration PROM | EPROM (OTP, UV-erasable window optional) |
| Taille de mémoire | 1 Mbit | 1 Mbit (1,048,576 bits) |
| Organisation de la mémoire | Serial (DCLK + DATA) | — |
| Tension d'alimentation | 3.0 V to 3.6 V | — |
| Supply Voltage (Typical) | 3.3 V | — |
| Interface | Altera PS Serial / JTAG (IEEE 1149.1) | — |
| Programmability | In-system via JTAG; OTP after programming | — |
| Standby Current | [DATA_NEEDED: standby current uA] | — |
| Active Current | [DATA_NEEDED: active current mA] | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range C] | — |
| Boîtier | 8-pin PDIP (PC8N suffix) | PDIP-8 (Plastic DIP, 8-pin, 0.1" pitch) |
| Type de montage | Through-Hole | Through-Hole (DIP socketable) |
| Statut RoHS | Compliant (PC8N suffix indicates lead-free) | — |
| Configuration Mode | Serial (PS mode) | — |
| JTAG Compliance | IEEE Std. 1149.1-1990 boundary-scan | — |
| Fonction | — | FPGA Configuration PROM |
| Configuration Interface | — | Altera Passive Serial (PS), 4-wire (nSTATUS, nCONFIG, DCLK, DATA0) |
| Supply Voltage VCC | — | 3.0 V to 3.6 V (typical 3.3 V) |
| Maximum DCLK Frequency | — | 17.6 MHz (17.6 Mb/s effective bitstream rate) |
| Plage de température de fonctionnement | — | [DATA_NEEDED: full industrial range from datasheet] |
| Cascade Support | — | Not supported in DIP-8 package (nCASC pin not exposed) |
| Programming Interface | — | JTAG via Altera Quartus / Quartus Prime ByteBlaster |
| Error Detection | — | Built-in CRC during configuration transfer |
| Niveau MSL | — | 1 (unlimited floor life) |
| Lead-Free / RoHS | — | Not lead-free (legacy Altera/Intel PC8 suffix is Sn-Pb finish); RoHS non-compliant variant |
| Compatible FPGA Families | — | ACEX 1K, APEX 20K, APEX II, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, FLEX 8000, MAX 7000B/AE/S, MAX 9000, Mercury, Stratix, Stratix II, Arria |
| Nombre de broches | — | 8 |