EPC2C20 vs EPC2LI20NGA Comparaison
Comparaison détaillée côte à côte de EPC2C20 par Altera et EPC2LI20NGA par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPC2C20 | EPC2LI20NGA |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $4,35 |
| Manufacturer | Altera | Altera / Intel PSG |
| MPN | EPC2C20 | — |
| Device Type | Configuration device integrated circuit | — |
| Primary Function | Configuration of SRAM-based lookup-table devices | — |
| Configuration Architecture | Single-device configuration solution | — |
| Architecture Block 1 | Configuration controller | — |
| Architecture Block 2 | Flash memory | — |
| Memory Technology | Flash memory | — |
| Supported Device Class | SRAM-based LUT devices | — |
| Configuration Mode | [DATA_NEEDED: configuration mode] | — |
| Memory Density | [DATA_NEEDED: memory density] | — |
| Configuration Data Interface | [DATA_NEEDED: configuration data interface] | — |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Configuration Clock Frequency | [DATA_NEEDED: configuration clock frequency] | — |
| Boîtier | [DATA_NEEDED: package] | 20-PLCC (9x9 mm) |
| Nombre de broches | [DATA_NEEDED: pin count] | — |
| Plage de température de fonctionnement | [DATA_NEEDED: operating temperature range] | -40C to +85C (Industrial) |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Compliant (lead-free 'G' suffix) |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Taille de mémoire | — | 1.6 Mbit |
| Fonction | — | In-System Programmable Configuration PROM |
| Target Device | — | SRAM-based LUT FPGAs |
| Tension d'alimentation | — | 3.0 V to 3.6 V (3.3 V typical) |
| Configuration Interface | — | Passive Serial / Passive Parallel |
| Programming Method | — | In-System via JTAG (IEEE 1149.1) |
| Cascadable | — | Yes (DATA, DCLK chain) |
| Type de montage | — | Surface Mount / Thru-Hole Socket |
| Lead-Free Termination | — | Yes (NiPdAu) |
| Process Technology | — | CMOS EEPROM |
| Datasheet Document | — | EPC2 datasheet (Altera) |