EPC2C20 vs EPC2LI20NGA Vergleich
Detaillierter Direktvergleich von EPC2C20 von Altera und EPC2LI20NGA von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPC2C20 | EPC2LI20NGA |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Aktiv | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $0,00 | $4,35 |
| Manufacturer | Altera | Altera / Intel PSG |
| MPN | EPC2C20 | — |
| Device Type | Configuration device integrated circuit | — |
| Primary Function | Configuration of SRAM-based lookup-table devices | — |
| Configuration Architecture | Single-device configuration solution | — |
| Architecture Block 1 | Configuration controller | — |
| Architecture Block 2 | Flash memory | — |
| Memory Technology | Flash memory | — |
| Supported Device Class | SRAM-based LUT devices | — |
| Configuration Mode | [DATA_NEEDED: configuration mode] | — |
| Memory Density | [DATA_NEEDED: memory density] | — |
| Configuration Data Interface | [DATA_NEEDED: configuration data interface] | — |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Configuration Clock Frequency | [DATA_NEEDED: configuration clock frequency] | — |
| Gehäuse | [DATA_NEEDED: package] | 20-PLCC (9x9 mm) |
| Pin-Anzahl | [DATA_NEEDED: pin count] | — |
| Betriebstemperaturbereich | [DATA_NEEDED: operating temperature range] | -40C to +85C (Industrial) |
| RoHS-Status | [DATA_NEEDED: RoHS status] | Compliant (lead-free 'G' suffix) |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Speichergröße | — | 1.6 Mbit |
| Funktion | — | In-System Programmable Configuration PROM |
| Target Device | — | SRAM-based LUT FPGAs |
| Versorgungsspannung | — | 3.0 V to 3.6 V (3.3 V typical) |
| Configuration Interface | — | Passive Serial / Passive Parallel |
| Programming Method | — | In-System via JTAG (IEEE 1149.1) |
| Cascadable | — | Yes (DATA, DCLK chain) |
| Montageart | — | Surface Mount / Thru-Hole Socket |
| Lead-Free Termination | — | Yes (NiPdAu) |
| Process Technology | — | CMOS EEPROM |
| Datasheet Document | — | EPC2 datasheet (Altera) |