EPC2C20 vs EPC2LI20NGA Comparación
Comparación detallada lado a lado de EPC2C20 por Altera y EPC2LI20NGA por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPC2C20 | EPC2LI20NGA |
|---|---|---|
| Marca | Altera | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Activo | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $0,00 | $4,35 |
| Manufacturer | Altera | Altera / Intel PSG |
| MPN | EPC2C20 | — |
| Device Type | Configuration device integrated circuit | — |
| Primary Function | Configuration of SRAM-based lookup-table devices | — |
| Configuration Architecture | Single-device configuration solution | — |
| Architecture Block 1 | Configuration controller | — |
| Architecture Block 2 | Flash memory | — |
| Memory Technology | Flash memory | — |
| Supported Device Class | SRAM-based LUT devices | — |
| Configuration Mode | [DATA_NEEDED: configuration mode] | — |
| Memory Density | [DATA_NEEDED: memory density] | — |
| Configuration Data Interface | [DATA_NEEDED: configuration data interface] | — |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Configuration Clock Frequency | [DATA_NEEDED: configuration clock frequency] | — |
| Encapsulado | [DATA_NEEDED: package] | 20-PLCC (9x9 mm) |
| Recuento de pines | [DATA_NEEDED: pin count] | — |
| Rango de temperatura de funcionamiento | [DATA_NEEDED: operating temperature range] | -40C to +85C (Industrial) |
| Estado RoHS | [DATA_NEEDED: RoHS status] | Compliant (lead-free 'G' suffix) |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Tamaño de memoria | — | 1.6 Mbit |
| Función | — | In-System Programmable Configuration PROM |
| Target Device | — | SRAM-based LUT FPGAs |
| Tensión de alimentación | — | 3.0 V to 3.6 V (3.3 V typical) |
| Configuration Interface | — | Passive Serial / Passive Parallel |
| Programming Method | — | In-System via JTAG (IEEE 1149.1) |
| Cascadable | — | Yes (DATA, DCLK chain) |
| Tipo de montaje | — | Surface Mount / Thru-Hole Socket |
| Lead-Free Termination | — | Yes (NiPdAu) |
| Process Technology | — | CMOS EEPROM |
| Datasheet Document | — | EPC2 datasheet (Altera) |