EPF10K250EFC672-2 vs EPF10K250EFI672-3 Comparaison
Comparaison détaillée côte à côte de EPF10K250EFC672-2 par Intel et EPF10K250EFI672-3 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPF10K250EFC672-2 | EPF10K250EFI672-3 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $108,00 | $125,00 |
| Family | FLEX 10KE | FLEX 10KE |
| Logic Elements | 12,480 | [DATA_NEEDED: exact LE count] |
| Typical Gates | 250,000 | 250,000 |
| Embedded Array Blocks (EABs) | 20 | 12 |
| Maximum User RAM Bits | 40,960 | — |
| User I/Os | 470 | — |
| Boîtier | 672-BGA (FineLine BGA), 45 x 45 mm, 1.27 mm pitch | 672-ball FineLine BGA, 1.27 mm pitch |
| Nombre de broches | 672 | — |
| Propagation Delay | 0.4 ns | — |
| Température de fonctionnement | 0 C to +70 C (Commercial) | 0 °C to 70 °C (commercial) |
| Core Supply Voltage | 2.3 V (typical 2.5 V) | 2.5 V |
| I/O Standard Support | 1.8 V, 2.5 V, 3.3 V (multi-volt I/O) | — |
| Logic Family | CMOS, SRAM-based | — |
| Configuration | SRAM, in-system programmable (ISP) via JTAG | — |
| Boundary Scan | IEEE 1149.1 (JTAG) compliant | — |
| Type de montage | Surface Mount | — |
| Statut RoHS | Non-RoHS Compliant (per Fly-Wing listing) | Unknown (legacy Altera non-RoHS device) |
| User I/O Pins | — | 470 |
| EAB Dual-Port Width | — | Up to 16-bit |
| Maximum EAB Memory | — | [DATA_NEEDED: bits per EAB] |
| Propagation Delay (tpd) | — | 0.4 ns (typical, -3 speed grade) |
| I/O Supply Voltage | — | 2.5 V / 3.3 V (multiVolt I/O) |
| Process Technology | — | CMOS, SRAM-based configuration |
| Configuration Interface | — | JTAG / ByteBlaster (EPC2/EPC8 PROM) |
| Design Entry | — | EDIF 2 0 0 / 3 0 0, LPM, VHDL, Verilog |