EPF10K30EQC208-2 vs EPF10K30EQC208-1X Comparaison
Comparaison détaillée côte à côte de EPF10K30EQC208-2 par Intel et EPF10K30EQC208-1X par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Intel
EPF10K30EQC208-1X - 30K-Gate FLEX 10KE FPGA, 147 I/O, PQFP-208 | Intel
EPF10K30EQC208-1X ObsoleteComparaison des spécifications
| Paramètre | EPF10K30EQC208-2 | EPF10K30EQC208-1X |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $17,85 | $18,40 |
| Family | FLEX 10KE | FLEX 10KE (Altera/Intel legacy FPGA) |
| Logic Elements | 1,728 | — |
| Typical Gates | 30,000 | — |
| Logic Array Blocks (LABs) | 216 | 216 |
| Embedded Array Blocks (EABs) | 6 (24 Kbits total) | — |
| Embedded Memory (bits) | 24,576 | — |
| Maximum User I/O | 147 | — |
| Process Technology | 0.22 µm CMOS | 0.22 um CMOS, SRAM-based |
| Core Supply Voltage | 2.5 V | — |
| Speed Grade | -2 | — |
| Température de fonctionnement | Commercial (0 °C to +70 °C) | 0 C to 70 C (commercial) |
| Boîtier | 208-pin PQFP (Plastic Quad Flat Pack) | 208-pin BFQFP / PQFP (28 x 28 mm) |
| Package Dimensions | 30.60 mm × 30.60 mm, 0.50 mm pitch | — |
| Maximum Internal Frequency | 200 MHz | — |
| Type de montage | Surface Mount (gull-wing leads) | Surface Mount (gull-wing) |
| Programmability | SRAM-based, JTAG/ISP | — |
| Statut RoHS | Non-compliant (legacy PQFP package) | — |
| Series | — | FLEX 10KE |
| Logic Elements / Cells | — | 1,728 |
| Typical Gate Count | — | 30,000 gates |
| Total RAM Bits | — | 24,576 bits |
| Number of I/O Pins | — | 147 |
| Core Voltage (VCCINT) | — | 2.375 V to 2.625 V (2.5 V nominal) |
| I/O Voltage (VCCIO) | — | 3.3 V (multi-standard I/O) |
| Internal Frequency (typical) | — | 250 MHz (per distributor data; fabric-dependent) |
| Propagation Delay | — | 0.6 ns (per DigChip) |
| Programming Interface | — | JTAG (IEEE 1149.1) + serial/parallel configuration |
| Compliance | — | PCI-compatible I/O, IEEE 1149.1 boundary scan |