EPF10K50ETC144-3 vs EPF10K30ETC144-2 Comparaison
Comparaison détaillée côte à côte de EPF10K50ETC144-3 par Intel et EPF10K30ETC144-2 par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPF10K50ETC144-3 | EPF10K30ETC144-2 |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $29,90 | $37,80 |
| Family | FLEX 10KE | FLEX 10KE |
| Typical Gate Count | 50,000 gates | — |
| Logic Elements / Cells | 2,880 | — |
| Total Memory Bits | 40,960 bits | — |
| Logic Array Blocks (LABs) | 360 | 216 |
| User I/O Pins (this package) | 102 | — |
| Max User I/O (family) | 274 pins | — |
| Nombre de broches | 144 | — |
| Package Type | TQFP-144 (also referred to as 144-LQFP) | — |
| Propagation Delay | 0.6 ns | — |
| Maximum Internal Frequency | 166.67 MHz | — |
| Internal Frequency (per DigChip summary) | 66.67 MHz | — |
| Process Technology | 0.22 µm CMOS | CMOS, SRAM-based |
| Core Supply Voltage | 2.5 V | — |
| Logic Family | CMOS | — |
| Température de fonctionnement | 0 °C to +70 °C (Commercial) | 0C to +70C (Commercial) |
| Type de montage | Surface Mount | Surface Mount |
| Configuration Memory | SRAM (volatile) | — |
| JTAG Support | IEEE 1149.1 boundary scan | — |
| Statut RoHS | [DATA_NEEDED: rohs status] | Compliant (lead-free) |
| Series | — | FLEX 10KE |
| Logic Elements | — | 1,728 |
| Typical Gates | — | 30,000 |
| Maximum User I/Os | — | 102 |
| Embedded Memory Bits | — | 24,576 |
| Embedded Array Blocks (EABs) | — | 6 |
| Boîtier | — | 144-LQFP (TQFP, 20x20 mm) |
| Speed Grade | — | -2 |
| Core Voltage (VCCINT) | — | 2.5 V (2.375 V to 2.625 V) |
| I/O Voltage (VCCIO) | — | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| Internal Frequency | — | up to 80 MHz |
| Propagation Delay (typ.) | — | 0.6 ns |
| Configuration Method | — | SRAM, JTAG (IEEE 1149.1) |