EPM240GM100I5N vs EPM240M100C4N Comparaison
Comparaison détaillée côte à côte de EPM240GM100I5N par Intel et EPM240M100C4N par Intel. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM240GM100I5N | EPM240M100C4N |
|---|---|---|
| Marque | Intel | Intel |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $39,77 | $7,45 |
| Family | MAX II | — |
| Logic Elements (LE) | 240 | — |
| Equivalent Macrocells | 192 | — |
| User I/O Pins | 80 | — |
| User Flash Memory (UFM) | 8 Kbits | — |
| Pin-to-Pin Delay (tPD1) | 4.7 ns | — |
| Maximum Operating Frequency | 300 MHz (internal) | — |
| Process Technology | 0.18 µm 6-layer-metal flash CMOS | — |
| Configuration Memory | On-chip non-volatile flash (instant-on) | Non-volatile on-chip flash (instant-on) |
| Supply Voltage - Core (VCCINT) | 1.8 V | — |
| MultiVolt I/O (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V / 5 V | — |
| Boîtier | 100-ball Micro FineLine BGA (MBGA), 6 mm × 6 mm, 0.5 mm pitch | 100-pin Micro FineLine BGA (MBGA), 6 x 6 mm, 0.5 mm pitch |
| Température de fonctionnement | -40 °C to +105 °C (industrial) | -40 C to +125 C (industrial) |
| Type de montage | Surface Mount | Surface Mount (BGA) |
| RoHS / Lead-Free | Lead-free per package marking | — |
| Programming Interface | JTAG (IEEE 1149.1) ISP | — |
| Series | — | MAX II |
| Device Family | — | EPM240 |
| Macro Cells | — | 192 |
| User I/Os | — | 80 |
| Propagation Delay (tPD) Max | — | 4.7 ns |
| Internal Operating Frequency | — | 247.5 MHz |
| Supply Voltage - Core | — | 2.5 V / 3.3 V |
| I/O Standards Supported | — | 1.5 V, 1.8 V, 2.5 V, 3.3 V LVCMOS/LVTTL |
| User Flash Memory | — | 8 Kbit |
| Programmability | — | In-System Programmable via JTAG (IEEE 1149.1) |
| Logic Family | — | CMOS |
| Statut RoHS | — | Lead Free (per DigiChip spec sheet) |
| Logic Array Blocks (LABs) | — | 4 (16 macrocells per LAB) |
| MultiTrack Interconnect | — | Yes |
| Hot Socketing | — | Yes |