EPM3512AQC208-10N vs EPM3512AQC208-10S Comparaison
Comparaison détaillée côte à côte de EPM3512AQC208-10N par Intel et EPM3512AQC208-10S par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM3512AQC208-10N | EPM3512AQC208-10S |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $42,80 | $9,75 |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Usable Gates | Up to 10,000 | 1750 |
| Logic Array Blocks (LABs) | 16 | 32 (16 macrocells each) |
| User I/Os | 172 | 208 |
| Boîtier | 208-pin PQFP (Plastic Quad Flat Pack) | 208-pin FineLine BGA-256 |
| Tension d'alimentation | 3.3 V | — |
| Pin-to-Pin Delay | 4.5 ns (-10 speed grade) | — |
| Maximum Internal Frequency | 227.3 MHz | — |
| Speed Grade | -10 | -10 (tPD1 = 7.5 ns) |
| Process Technology | CMOS EEPROM | EEPROM-based CMOS |
| In-System Programming | IEEE Std. 1149.1 JTAG, IEEE Std. 1532 | — |
| Boundary-Scan Test (BST) | Built-in, IEEE 1149.1 compliant | — |
| I/O Standards | MultiVolt (1.8V / 2.5V / 3.3V) | — |
| Température de fonctionnement | 0 C to 70 C (commercial) | 0C to +70C (commercial) |
| Statut RoHS | [DATA_NEEDED: RoHS status not in verified web data] | [DATA_NEEDED: rohs_status] |
| Propagation Delay (tPD1) | — | 7.5 ns (pin-to-pin) |
| Supply Voltage - VCCINT (internal) | — | 3.3 V |
| Supply Voltage - VCCIO (I/O) | — | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) |
| Programming Technology | — | CMOS EEPROM |
| In-System Programmability (ISP) | — | Yes (IEEE Std. 1149.1 JTAG) |
| PCI Compliance | — | Yes (PCI Local Bus Specification Rev 2.2) |
| Boundary-Scan (JTAG) | — | Yes (1149.1 compliant) |
| Program/Erase Endurance | — | 100 cycles minimum |
| Logic Family | — | CMOS |