EPM3512AQC208-2 vs EPM3512AQC208-10S Comparaison
Comparaison détaillée côte à côte de EPM3512AQC208-2 par Altera et EPM3512AQC208-10S par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM3512AQC208-2 | EPM3512AQC208-10S |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $18,75 | $9,75 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| User I/O Pins | 172 | — |
| Logic Array Blocks (LABs) | 16 | 32 (16 macrocells each) |
| Speed Grade | -2 | -10 (tPD1 = 7.5 ns) |
| Boîtier | PQFP-208 (QC) | 208-pin FineLine BGA-256 |
| Supply Voltage (Core) | 3.3 V | — |
| Output Drive Voltage | 2.5 V / 3.3 V programmable | — |
| Input Voltage Tolerance | 2.5 V / 3.3 V / 5.0 V | — |
| Process Technology | 0.30 µm EEPROM | EEPROM-based CMOS |
| Program/Erase Endurance | 100 cycles (typical) | 100 cycles minimum |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| User I/O Banks | 4 | — |
| Plage de température de fonctionnement | Commercial (0C to +70C) | — |
| Type de montage | Surface Mount | — |
| Statut RoHS | Non-compliant (legacy PQFP) | [DATA_NEEDED: rohs_status] |
| Lead-Free | No (SnPb lead finish) | — |
| Security Bit | Yes (programmable) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 1750 |
| User I/Os | — | 208 |
| Propagation Delay (tPD1) | — | 7.5 ns (pin-to-pin) |
| Supply Voltage - VCCINT (internal) | — | 3.3 V |
| Supply Voltage - VCCIO (I/O) | — | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) |
| Programming Technology | — | CMOS EEPROM |
| In-System Programmability (ISP) | — | Yes (IEEE Std. 1149.1 JTAG) |
| PCI Compliance | — | Yes (PCI Local Bus Specification Rev 2.2) |
| Température de fonctionnement | — | 0C to +70C (commercial) |
| Boundary-Scan (JTAG) | — | Yes (1149.1 compliant) |
| Logic Family | — | CMOS |