EPM3512AQC208-7N vs EPM3512AQC208-10S Comparaison
Comparaison détaillée côte à côte de EPM3512AQC208-7N par Altera et EPM3512AQC208-10S par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM3512AQC208-7N - 512-Macro MAX 3000A CPLD, 208-PQFP | Altera
EPM3512AQC208-7N ⚠ Dernier achat
Comparaison des spécifications
| Paramètre | EPM3512AQC208-7N | EPM3512AQC208-10S |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Dernier achat | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $41,41 | $9,75 |
| Family | MAX 3000A | MAX 3000A |
| Logic Capacity | 512 macrocells, 10,000 usable gates | — |
| Logic Array Blocks (LABs) | 32 | 32 (16 macrocells each) |
| Macrocells per LAB | 16 | — |
| User I/Os | 172 | 208 |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Frequency (fCNT) | 116.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V (3.0 V to 3.6 V) | — |
| I/O Bank Count | 4 (MultiVolt) | — |
| Supported I/O Standards | 1.8 V / 2.5 V / 3.3 V LVTTL/LVCMOS | — |
| Process Technology | 0.30 µm CMOS EEPROM | EEPROM-based CMOS |
| Configuration | Non-volatile EEPROM, in-system programmable (ISP) | — |
| JTAG Interface | IEEE 1149.1 BST + IEEE 1532 ISP | — |
| Boîtier | 208-Pin PQFP / FQFP-208 (Plastic Quad Flat Pack, gull-wing) | 208-pin FineLine BGA-256 |
| Température de fonctionnement | 0 °C to +70 °C (commercial) | 0C to +70C (commercial) |
| Statut RoHS | Compliant | [DATA_NEEDED: rohs_status] |
| Speed Grade | -7 | -10 (tPD1 = 7.5 ns) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 512 |
| Usable Gates | — | 1750 |
| Propagation Delay (tPD1) | — | 7.5 ns (pin-to-pin) |
| Supply Voltage - VCCINT (internal) | — | 3.3 V |
| Supply Voltage - VCCIO (I/O) | — | 2.5 V, 3.3 V, or 5.0 V (MultiVolt) |
| Programming Technology | — | CMOS EEPROM |
| In-System Programmability (ISP) | — | Yes (IEEE Std. 1149.1 JTAG) |
| PCI Compliance | — | Yes (PCI Local Bus Specification Rev 2.2) |
| Boundary-Scan (JTAG) | — | Yes (1149.1 compliant) |
| Program/Erase Endurance | — | 100 cycles minimum |
| Logic Family | — | CMOS |