EPM5032DC vs EPM5032DC-25 Comparaison
Comparaison détaillée côte à côte de EPM5032DC par Altera et EPM5032DC-25 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5032DC | EPM5032DC-25 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $10,40 | $3,55 |
| Family | MAX 5000 | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV Erasable Programmable Logic Device (EPLD) |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 1 | — |
| Boîtier | DIP-24 (ceramic, windowed) | CDIP-28 (Windowed Ceramic DIP-28) |
| Speed Grade | DC (commercial) | — |
| Température de fonctionnement | 0C to +70C | [DATA_NEEDED: operating temperature range] |
| Technology | Bipolar EPROM, UV-erasable | — |
| Programmable Logic Elements | AND array + fixed OR array per macrocell | — |
| Configuration Memory | EPROM (UV-erasable via package window) | — |
| Type de montage | Through-hole (DIP) | — |
| Nombre de broches | 24 | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Lead Free / RoHS Compliant (per distributor listings) |
| Programming Tool | Altera MAX+PLUS II / A+PLUS legacy | — |
| Statut du cycle de vie | Obsolete (mature legacy) | — |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |
| Product Family | — | MAX 5000 |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Maximum Counter Frequency (fCNT) | — | [DATA_NEEDED: maximum counter frequency] |
| Setup Time (tSU) | — | [DATA_NEEDED: setup time] |
| Number of Dedicated Inputs | — | 32 (in DIP-28 pinout) |
| Number of I/O Pins | — | 22 (in DIP-28 pinout, 4 used as dedicated inputs) |
| Process Technology | — | CMOS, EPROM (UV-Erasable) |
| Architecture | — | PAL-Type, Single-LAB, 32-Macrocell |
| Output Structure | — | Programmable I/O with output enable |
| Flip-Flop Configuration | — | D, T, JK, or SR (programmable) |
| Programming Method | — | UV erase + Altera/Intel MAX+PLUS II programmer |
| Erasure Method | — | UV light through ceramic window |