EPM5032DC vs EPM5032DC-25 Comparison

Detailed side-by-side comparison of EPM5032DC by Altera and EPM5032DC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5032DC EPM5032DC-25
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Family MAX 5000 —
Device Type EPLD (Erasable Programmable Logic Device) UV Erasable Programmable Logic Device (EPLD)
Macrocells 32 32
Logic Array Blocks (LABs) 1 —
Package DIP-24 (ceramic, windowed) CDIP-28 (Windowed Ceramic DIP-28)
Speed Grade DC (commercial) —
Operating Temperature 0C to +70C [DATA_NEEDED: operating temperature range]
Technology Bipolar EPROM, UV-erasable —
Programmable Logic Elements AND array + fixed OR array per macrocell —
Configuration Memory EPROM (UV-erasable via package window) —
Mounting Type Through-hole (DIP) —
Pin Count 24 —
RoHS Status [DATA_NEEDED: RoHS status] Lead Free / RoHS Compliant (per distributor listings)
Programming Tool Altera MAX+PLUS II / A+PLUS legacy —
Lifecycle Status Obsolete (mature legacy) —
Manufacturer — Altera (Intel Programmable Solutions Group)
Product Family — MAX 5000
Pin-to-Pin Propagation Delay (tPD) — 25 ns
Maximum Counter Frequency (fCNT) — [DATA_NEEDED: maximum counter frequency]
Setup Time (tSU) — [DATA_NEEDED: setup time]
Number of Dedicated Inputs — 32 (in DIP-28 pinout)
Number of I/O Pins — 22 (in DIP-28 pinout, 4 used as dedicated inputs)
Process Technology — CMOS, EPROM (UV-Erasable)
Architecture — PAL-Type, Single-LAB, 32-Macrocell
Output Structure — Programmable I/O with output enable
Flip-Flop Configuration — D, T, JK, or SR (programmable)
Programming Method — UV erase + Altera/Intel MAX+PLUS II programmer
Erasure Method — UV light through ceramic window

Datasheets & Resources

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