EPM5032DC vs EPM5032DC-25 比較
詳細な並列比較: EPM5032DC メーカー: Altera および EPM5032DC-25 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5032DC | EPM5032DC-25 |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | NRND |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $10.40 | $3.55 |
| Family | MAX 5000 | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | UV Erasable Programmable Logic Device (EPLD) |
| Macrocells | 32 | 32 |
| Logic Array Blocks (LABs) | 1 | — |
| パッケージ | DIP-24 (ceramic, windowed) | CDIP-28 (Windowed Ceramic DIP-28) |
| Speed Grade | DC (commercial) | — |
| 動作温度 | 0C to +70C | [DATA_NEEDED: operating temperature range] |
| Technology | Bipolar EPROM, UV-erasable | — |
| Programmable Logic Elements | AND array + fixed OR array per macrocell | — |
| Configuration Memory | EPROM (UV-erasable via package window) | — |
| 実装タイプ | Through-hole (DIP) | — |
| ピン数 | 24 | — |
| RoHS ステータス | [DATA_NEEDED: RoHS status] | Lead Free / RoHS Compliant (per distributor listings) |
| Programming Tool | Altera MAX+PLUS II / A+PLUS legacy | — |
| ライフサイクル状態 | Obsolete (mature legacy) | — |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |
| Product Family | — | MAX 5000 |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Maximum Counter Frequency (fCNT) | — | [DATA_NEEDED: maximum counter frequency] |
| Setup Time (tSU) | — | [DATA_NEEDED: setup time] |
| Number of Dedicated Inputs | — | 32 (in DIP-28 pinout) |
| Number of I/O Pins | — | 22 (in DIP-28 pinout, 4 used as dedicated inputs) |
| Process Technology | — | CMOS, EPROM (UV-Erasable) |
| Architecture | — | PAL-Type, Single-LAB, 32-Macrocell |
| Output Structure | — | Programmable I/O with output enable |
| Flip-Flop Configuration | — | D, T, JK, or SR (programmable) |
| Programming Method | — | UV erase + Altera/Intel MAX+PLUS II programmer |
| Erasure Method | — | UV light through ceramic window |