EPM5128JI vs EPM5128JC Comparaison
Comparaison détaillée côte à côte de EPM5128JI par Intel et EPM5128JC par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5128JI | EPM5128JC |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $23,95 | $9,75 |
| Device Family | MAX 5000 | — |
| Device Type | UV-erasable programmable logic device (PLD) | EPLD / CPLD |
| Macrocells | 128 | — |
| Propagation Delay (tPD) | 55 ns (typical) | 35 ns |
| Maximum Internal Frequency | 40 MHz | — |
| Process Technology | CMOS | CMOS EPROM |
| Programmable Technology | UV-erasable EPROM cell | — |
| Boîtier | 68-terminal ceramic CQCC, windowed, J-leads | — |
| Operating Temperature Grade | Industrial ("I" suffix) | — |
| Programming | Altera MAX+plus II compatible programmer + UV eraser | — |
| Statut RoHS | Non-compliant (ceramic hermetic package) | [DATA_NEEDED: RoHS status - legacy part] |
| Lead Finish | Tin-lead (SnPb) over nickel | — |
| Type de montage | Surface Mount (J-lead CQCC) | Surface Mount (PLCC socket or solder) |
| Logic Blocks | [DATA_NEEDED: number of LABs / logic array blocks] | — |
| User I/O Pins | [DATA_NEEDED: pin count of user I/Os] | [DATA_NEEDED: user I/O pin count] |
| Tension d'alimentation | [DATA_NEEDED: VCC range] | — |
| Standby Current | [DATA_NEEDED: ICCSB] | — |
| Product Family | — | MAX 5000 |
| Macrocell Count | — | 128 |
| Logic Elements | — | Programmable AND/OR/XOR array |
| Supply Voltage (VCC) | — | 5 V (typical) |
| Nombre de broches | — | 68 |
| Package Type | — | PLCC-68 (JLCC) ceramic, J-leaded |
| Dedicated Inputs | — | 8 |
| Configuration Memory | — | UV-erasable EPROM (windowed package) |
| Programming Interface | — | Altera MAX+PLUS II / A+PLUS / legacy programmer |
| Température de fonctionnement | — | Commercial 0C to +70C |
| Boundary Scan | — | JTAG IEEE 1149.1 (family feature) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |