EPM5128JI vs EPM5128JC Сравнение
Подробное сравнение бок о бок EPM5128JI от Intel и EPM5128JC от Altera. Сравните ключевые характеристики, электрические параметры, упаковку, статус жизненного цикла, цены и наличие, чтобы выбрать лучший компонент для ваших требований.
Сравнение характеристик
| Параметр | EPM5128JI | EPM5128JC |
|---|---|---|
| Бренд | Intel | Altera |
| Категория | FPGA & CPLD | FPGA & CPLD |
| Статус жизненного цикла | Obsolete | Obsolete |
| Наличие | In Stock | In Stock |
| Цена за единицу (USD) | $23,95 | $9,75 |
| Device Family | MAX 5000 | — |
| Device Type | UV-erasable programmable logic device (PLD) | EPLD / CPLD |
| Macrocells | 128 | — |
| Propagation Delay (tPD) | 55 ns (typical) | 35 ns |
| Maximum Internal Frequency | 40 MHz | — |
| Process Technology | CMOS | CMOS EPROM |
| Programmable Technology | UV-erasable EPROM cell | — |
| Корпус | 68-terminal ceramic CQCC, windowed, J-leads | — |
| Operating Temperature Grade | Industrial ("I" suffix) | — |
| Programming | Altera MAX+plus II compatible programmer + UV eraser | — |
| Статус RoHS | Non-compliant (ceramic hermetic package) | [DATA_NEEDED: RoHS status - legacy part] |
| Lead Finish | Tin-lead (SnPb) over nickel | — |
| Тип монтажа | Surface Mount (J-lead CQCC) | Surface Mount (PLCC socket or solder) |
| Logic Blocks | [DATA_NEEDED: number of LABs / logic array blocks] | — |
| User I/O Pins | [DATA_NEEDED: pin count of user I/Os] | [DATA_NEEDED: user I/O pin count] |
| Напряжение питания | [DATA_NEEDED: VCC range] | — |
| Standby Current | [DATA_NEEDED: ICCSB] | — |
| Product Family | — | MAX 5000 |
| Macrocell Count | — | 128 |
| Logic Elements | — | Programmable AND/OR/XOR array |
| Supply Voltage (VCC) | — | 5 V (typical) |
| Количество выводов | — | 68 |
| Package Type | — | PLCC-68 (JLCC) ceramic, J-leaded |
| Dedicated Inputs | — | 8 |
| Configuration Memory | — | UV-erasable EPROM (windowed package) |
| Programming Interface | — | Altera MAX+PLUS II / A+PLUS / legacy programmer |
| Рабочая температура | — | Commercial 0C to +70C |
| Boundary Scan | — | JTAG IEEE 1149.1 (family feature) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |