EPM5130JC-1 vs EPM5128JC-2 Comparaison
Comparaison détaillée côte à côte de EPM5130JC-1 par Altera et EPM5128JC-2 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5130JC-1 | EPM5128JC-2 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,25 | $21,75 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | MAX 5000 |
| Usable Gates | 2,500 gates | — |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Propagation Delay (tPD) | 40 ns | 45 ns (max) |
| Supply Voltage (VCC) | 5 V | — |
| Dedicated Inputs | 19 | 7 |
| I/O Pins | 80 | — |
| Boîtier | 84-pin PLCC (J-lead) | 68-pin CQCC (Ceramic Quad Flat Pack), windowed |
| Type de montage | Surface Mount | Surface Mount |
| Programming Technology | UV-erasable EPROM (quartz window) | — |
| Process Technology | CMOS | CMOS |
| Température de fonctionnement | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| External Clock Pins | 1 global clock | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | Non-compliant (ceramic windowed package contains lead-bearing solder) |
| Device Type | — | UV-Erasable Programmable Logic Device (PLD) |
| Maximum Counter Frequency (fCNT) | — | 50 MHz |
| Input Setup Time (tSU) | — | 7.5 ns |
| Output Drive Current (IOH/IOL) | — | 12 mA DC |
| Tension d'alimentation | — | 5 V (nominal) |
| Program/Erase Method | — | UV (ceramic window) |
| Erase/Program Cycles | — | [DATA_NEEDED: minimum erase/program cycles] |
| Logic Family | — | TTL-compatible I/O |