EPM5130JC-1 vs EPM5128JC-2 对比
详细并排对比 EPM5130JC-1 出自 Altera 和 EPM5128JC-2 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5130JC-1 | EPM5128JC-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $9.25 | $21.75 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | MAX 5000 |
| Usable Gates | 2,500 gates | — |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Propagation Delay (tPD) | 40 ns | 45 ns (max) |
| Supply Voltage (VCC) | 5 V | — |
| Dedicated Inputs | 19 | 7 |
| I/O Pins | 80 | — |
| 封装 | 84-pin PLCC (J-lead) | 68-pin CQCC (Ceramic Quad Flat Pack), windowed |
| 安装类型 | Surface Mount | Surface Mount |
| Programming Technology | UV-erasable EPROM (quartz window) | — |
| Process Technology | CMOS | CMOS |
| 工作温度 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| External Clock Pins | 1 global clock | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance] | Non-compliant (ceramic windowed package contains lead-bearing solder) |
| Device Type | — | UV-Erasable Programmable Logic Device (PLD) |
| Maximum Counter Frequency (fCNT) | — | 50 MHz |
| Input Setup Time (tSU) | — | 7.5 ns |
| Output Drive Current (IOH/IOL) | — | 12 mA DC |
| 电源电压 | — | 5 V (nominal) |
| Program/Erase Method | — | UV (ceramic window) |
| Erase/Program Cycles | — | [DATA_NEEDED: minimum erase/program cycles] |
| Logic Family | — | TTL-compatible I/O |