EPM5130WM883B-1 vs EPM5130GM883B Comparaison
Comparaison détaillée côte à côte de EPM5130WM883B-1 par Altera et EPM5130GM883B par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM5130WM883B-1 - 128-Macrocell UV PLD, 5V, CQFP-100 | Altera MAX 5000
EPM5130WM883B-1 Obsolete
Comparaison des spécifications
| Paramètre | EPM5130WM883B-1 | EPM5130GM883B |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $128,00 | $108,00 |
| Device Family | MAX 5000 (Classic EPLD) | — |
| Manufacturer | Altera (now Intel PSG) | Altera (now Intel Programmable Solutions Group) |
| Logic Type | UV-Erasable Programmable Logic Device (EPLD) | — |
| Technology | CMOS, EPROM cell | — |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | — |
| Dedicated Inputs | 19 | — |
| I/O Pins | 48 (bi-directional) | — |
| Propagation Delay (tPD) | 55 ns | — |
| Maximum Clock Frequency (fMAX) | 33.3 MHz | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) | — |
| External Clock Inputs | 1 global + shared inputs | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Package Type | CQFP-100, ceramic windowed (WM) | — |
| Military Screening | MIL-STD-883 Class B (883B suffix) | — |
| Température de fonctionnement | [DATA_NEEDED: military/industrial temperature grade] | -55C to +125C (MIL-STD-883B screening) |
| Programming Method | UV erase + EPROM programming | — |
| Statut RoHS | [DATA_NEEDED: confirmed RoHS for ceramic windowed CQFP] | [DATA_NEEDED: RoHS compliance status] |
| Type de montage | Surface Mount (CQFP with J-leads) | Through-Hole (Pin Grid Array) |
| Series | — | MAX 5000 |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Usable Gates | — | 5,000 |
| User I/O Pins | — | [DATA_NEEDED: maximum user I/O count] |
| Boîtier | — | 100-pin CPGA (S-CPGA-P100) |
| Nombre de broches | — | 100 |
| Tension d'alimentation | — | 5 V |
| Logic Family | — | CMOS, TTL-compatible |
| Configuration Memory | — | Non-volatile EEPROM |
| Propagation Delay | — | [DATA_NEEDED: tpd in ns] |
| Screening Level | — | MIL-STD-883B Class B |
| Lead Free Status | — | Lead free / RoHS Compliant (per ICComponents listing) |
| Programmable Security | — | Yes (security bit) |