EPM5192AGC vs EPM5192AJC-25 Comparaison
Comparaison détaillée côte à côte de EPM5192AGC par Altera et EPM5192AJC-25 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192AGC | EPM5192AJC-25 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $56,00 | $8,20 |
| Family | MAX 5000 (High-Speed, High-Density MAX 5000 Devices) | MAX 5000 EPLD |
| Device Type | UV-Erasable / OTP Complex PLD (EPLD) | — |
| Macrocells | 192 | 192 |
| Logic Density | High-density (per MAX 5000 family definition) | — |
| Architecture | CMOS, sum-of-products with macrocell output logic | — |
| Process Technology | CMOS | — |
| Boîtier | 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) | PLCC-68 (windowed ceramic, AJC) |
| Speed Grade Suffix | C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) | — |
| Température de fonctionnement | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: exact operating temperature range] |
| Programmability | UV-erasable (windowed package) / One-Time-Programmable (windowless variant) | — |
| Security Bit | Programmable security bit (per MAX 5000 family) | — |
| Tension d'alimentation | [DATA_NEEDED: VCC nominal and tolerance] | 5 V (typical) |
| Type de montage | Through-hole (Pin Grid Array) | Surface Mount |
| Statut RoHS | Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) | [DATA_NEEDED: RoHS compliance status] |
| Lifecycle | Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) | — |
| Programming Support | MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers | — |
| Manufacturer | — | Altera (now Intel PSG) |
| Propagation Delay (tPD) | — | 25 ns |
| Nombre de broches | — | 68 |
| Logic Blocks | — | MAX 5000 LABs (Logic Array Blocks) |
| Programmable Pins | — | [DATA_NEEDED: number of user I/O pins] |
| Erasure Method | — | UV-erasable (windowed ceramic package) |
| Programming Technology | — | EPROM (non-volatile) |
| Military Grade | — | Likely MIL-STD-883 processing per 'J' suffix in AJC marking (verify) |