EPM5192AGC vs EPM5192AJC-25 比較

詳細な並列比較: EPM5192AGC メーカー: Altera および EPM5192AJC-25 メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。

仕様比較

パラメータ EPM5192AGC EPM5192AJC-25
ブランド Altera Altera
カテゴリ FPGA & CPLD FPGA & CPLD
ライフサイクル状態 Obsolete Obsolete
在庫状況 In Stock In Stock
単価(USD) $56.00 $8.20
Family MAX 5000 (High-Speed, High-Density MAX 5000 Devices) MAX 5000 EPLD
Device Type UV-Erasable / OTP Complex PLD (EPLD) —
Macrocells 192 192
Logic Density High-density (per MAX 5000 family definition) —
Architecture CMOS, sum-of-products with macrocell output logic —
Process Technology CMOS —
パッケージ 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) PLCC-68 (windowed ceramic, AJC)
Speed Grade Suffix C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) —
動作温度 [DATA_NEEDED: operating temperature range] [DATA_NEEDED: exact operating temperature range]
Programmability UV-erasable (windowed package) / One-Time-Programmable (windowless variant) —
Security Bit Programmable security bit (per MAX 5000 family) —
電源電圧 [DATA_NEEDED: VCC nominal and tolerance] 5 V (typical)
実装タイプ Through-hole (Pin Grid Array) Surface Mount
RoHS ステータス Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) [DATA_NEEDED: RoHS compliance status]
Lifecycle Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) —
Programming Support MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers —
Manufacturer — Altera (now Intel PSG)
Propagation Delay (tPD) — 25 ns
ピン数 — 68
Logic Blocks — MAX 5000 LABs (Logic Array Blocks)
Programmable Pins — [DATA_NEEDED: number of user I/O pins]
Erasure Method — UV-erasable (windowed ceramic package)
Programming Technology — EPROM (non-volatile)
Military Grade — Likely MIL-STD-883 processing per 'J' suffix in AJC marking (verify)

データシート&リソース

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