EPM5192AGC vs EPM5192AJC-25 对比

详细并排对比 EPM5192AGC 出自 Altera 和 EPM5192AJC-25 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM5192AGC EPM5192AJC-25
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete Obsolete
库存状态 有库存 有库存
单价(USD) $56.00 $8.20
Family MAX 5000 (High-Speed, High-Density MAX 5000 Devices) MAX 5000 EPLD
Device Type UV-Erasable / OTP Complex PLD (EPLD) —
Macrocells 192 192
Logic Density High-density (per MAX 5000 family definition) —
Architecture CMOS, sum-of-products with macrocell output logic —
Process Technology CMOS —
封装 84-pin Ceramic PGA (Pin Grid Array, windowed or windowless) PLCC-68 (windowed ceramic, AJC)
Speed Grade Suffix C (commercial grade; specific pin-to-pin delay varies by base number -15/-20) —
工作温度 [DATA_NEEDED: operating temperature range] [DATA_NEEDED: exact operating temperature range]
Programmability UV-erasable (windowed package) / One-Time-Programmable (windowless variant) —
Security Bit Programmable security bit (per MAX 5000 family) —
电源电压 [DATA_NEEDED: VCC nominal and tolerance] 5 V (typical)
安装类型 Through-hole (Pin Grid Array) Surface Mount
RoHS 状态 Non-compliant (ceramic PGA contains lead; legacy military/industrial grade) [DATA_NEEDED: RoHS compliance status]
Lifecycle Obsolete (legacy Altera MAX 5000 family; maintained for long-lifecycle programs) —
Programming Support MAX+PLUS II legacy toolchain / Altera-compatible third-party programmers —
Manufacturer — Altera (now Intel PSG)
Propagation Delay (tPD) — 25 ns
引脚数量 — 68
Logic Blocks — MAX 5000 LABs (Logic Array Blocks)
Programmable Pins — [DATA_NEEDED: number of user I/O pins]
Erasure Method — UV-erasable (windowed ceramic package)
Programming Technology — EPROM (non-volatile)
Military Grade — Likely MIL-STD-883 processing per 'J' suffix in AJC marking (verify)

数据手册与资源

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