EPM5192AJM84-20 vs EPM5192AGC84-20 Comparaison
Comparaison détaillée côte à côte de EPM5192AJM84-20 par Altera et EPM5192AGC84-20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192AJM84-20 | EPM5192AGC84-20 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $171,00 | $41,20 |
| Manufacturer | Altera (now Intel) | — |
| Series | MAX 5000 (EPM5192) | — |
| Device Type | CMOS UV-Erasable/OTP Complex PLD | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| Programmable Interconnect | PIA (Programmable Interconnect Array) | — |
| Fréquence d'horloge maximale | 66.7 MHz | — |
| Propagation Delay (tPD) | 33 ns (speed grade -20) | — |
| Boîtier | 84-pin CQFP (S-CQCC-J84, J-lead) | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) |
| Terminal Form | J-Bend | — |
| Temperature Grade | MILITARY | — |
| Process Technology | CMOS EPROM (UV-erasable) | CMOS |
| Statut RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance] |
| Erasure Method | UV (quartz-windowed CQFP) or OTP | UV-Erasable (with OTP window) |
| Product Type | — | Complex Programmable Logic Device (CPLD) |
| Family | — | MAX 5000 |
| Logic Gates (typical) | — | [DATA_NEEDED: typical gate count] |
| Maximum Clock Frequency (fMAX) | — | 66.7 MHz |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Speed Grade | — | -20 |
| Package Code | — | WPGA |
| Operating Temperature Grade | — | Commercial |
| Tension d'alimentation | — | [DATA_NEEDED: VCC range] |
| I/O Standard | — | 5V CMOS / TTL compatible |
| Type de montage | — | Through-Hole (Pin Grid Array socket) |