EPM5192ALC84-15 vs EPM5192ALC84-20 Comparaison
Comparaison détaillée côte à côte de EPM5192ALC84-15 par Altera et EPM5192ALC84-20 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM5192ALC84-15 | EPM5192ALC84-20 |
|---|---|---|
| Marque | Altera | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $13,20 | $19,40 |
| Device Family | MAX 5000 (EPM5192) | — |
| Device Type | CPLD / UV-Erasable / OTP Complex PLD | UV-Erasable/OTP Complex PLD (EPLD) |
| Macrocells | 192 | 192 |
| Dedicated Inputs | 7 | — |
| User I/O Pins | 64 | — |
| Propagation Delay (tPD) | 15 ns | — |
| Propagation Delay (Industry Variant) | 25 ns (per MicrochipUSA listing) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (nominal 5 V) | — |
| Process Technology | CMOS (EPROM-based) | CMOS |
| Programmability | UV-erasable window / OTP | — |
| Boîtier | 84-pin PLCC (QCCJ, J-bend ceramic) | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Operating Temperature Grade | Commercial | — |
| Terminal Form | J-BEND | J-bend |
| Package Code | QCCJ | QCCJ (PLCC-84) |
| Package Shape | SQUARE | Square |
| Architecture | Programmable Logic Array + Macrocell Registers + PIA interconnect | — |
| Series | — | Altera MAX 5000 |
| Speed Grade | — | -20 (20 ns pin-to-pin delay) |
| Terminal Pitch | — | 1.270 mm |
| Temperature Grade | — | Commercial |
| Programming Method | — | UV-erase + EPROM (One-Time-Programmable option) |
| Logic Family | — | MAX 5000 EPLD |
| I/O Compatibility | — | TTL-compatible |
| Type de montage | — | Surface Mount (PLCC socket-compatible) |
| Configuration Memory | — | EPROM (UV-erasable) |
| Statut RoHS | — | [DATA_NEEDED: RoHS status not in provided web data] |