Altera

EPM9320ARC208-10 - MAX 9000 CPLD, 320 Macro, 10ns | Altera

Référence : EPM9320ARC208-10 ⚠ Dernier achat

En stock Expédié sous 1 à 3 jours ouvrés

5.0 V Vdss RQFP-208 (Power Quad Flat Pack) Package 144.9 MHz Speed

À partir de $21.4 USD / unité

MOQ : 1 |

Prix mis à jour : 2026-09-13

Tarifs dégressifs

Qté	Prix unitaire	Total
1	$38.5	$38,50
10	$33.2	$332,00
100	$28.75	$2 875,00
500	$24.9	$12 450,00
1 000	$21.4	$21 400,00

ℹ️ Tous les prix sont en USD

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EPM9320ARC208-10 Présentation

The Altera EPM9320ARC208-10 is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, delivering 320 macrocells with a 10 ns pin-to-pin logic delay in a 208-pin RQFP (Power Quad Flat Pack) package. The device integrates 6,000 usable gates and operates from a 5 V supply, offering 144.9 MHz maximum internal performance and in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface. The MAX 9000 architecture combines third-generation Multiple Array MatriX (MAX) technology with EEPROM configuration memory for instant-on, non-volatile behavior.

A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-style macrocell arrays on a single chip with a global interconnect fabric. CPLDs sit in the broader taxonomy: programmable logic -> CPLD/FPGA family -> non-volatile logic. They are valued for deterministic, predictable timing (no configuration load latency), high I/O count, and instant-on operation, making them complementary to SRAM-based FPGAs in glue-logic, bus-interface, and power-up sequencing roles.

Key features of the EPM9320ARC208-10 include programmable speed/power optimization (each macrocell can run at 50% or less power with only a nominal timing delay), JTAG-based IEEE 1149.1 boundary-scan test support, multi-voltage I/O compatibility, and built-in thermal management for the high-density RQFP package. The MAX 9000 family supports a wide range of package options including PLCC, RQFP, PGA, and BGA, all pin-compatible within a given package class for design flexibility.

The device is fabricated on a 5.0 V CMOS EEPROM process, providing non-volatile storage of the logic configuration. The 320-macrocell array with 16 LABs (Logic Array Blocks) provides predictable, deterministic timing suitable for state machines, address decoding, and synchronous control logic.

Typical applications include high-speed bus interface bridging, address decoding and chip-select generation, glue logic replacement for ASIC designs, industrial control systems, telecommunications infrastructure, and legacy system upgrades. The 5V tolerance makes it especially useful in industrial and telecom systems still based on 5V logic.

When designing with the EPM9320ARC208-10, perform a complete thermal analysis as recommended in Altera Application Note 74 (Evaluating Power for Altera Devices) before committing the design. The RQFP-208 package's power dissipation capability depends significantly on PCB layout, copper area, and airflow, so adequate thermal relief is essential for reliable high-speed operation.

This page synthesizes distributor stock status, drop-in MAX 9000 alternatives, and practical design notes not consolidated in any single manufacturer datasheet.

Alternatives de remplacement direct pour EPM9320ARC208-10 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.

Variantes de cette série

Modèles de la même série directement compatibles avec EPM9320ARC208-10 (même facteur de forme et même empreinte) — différant par Package, Operating Temperature, In-System Programmability, Architecture, Supply Voltage.

EPM9320ALC84-10

Intel

Package: 84-pin PLCC (J-Lead)

In-System Programmability: 5.0 V ISP via IEEE 1149.1 JTAG

Architecture: MAX (Multiple Array MatriX) with FastTrack Interconnect