EPM9560GI280-15 vs EPM9560GC280-15 Comparaison
Comparaison détaillée côte à côte de EPM9560GI280-15 par Intel et EPM9560GC280-15 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM9560GC280-15 - MAX 9000 CPLD, 560 Macro Cells, 15ns CPGA280 | Intel / Altera
EPM9560GC280-15 ObsoleteComparaison des spécifications
| Paramètre | EPM9560GI280-15 | EPM9560GC280-15 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | NRND | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $110,00 | $115,00 |
| Device Family | MAX 9000 | — |
| Architecture | CMOS EEPROM, third-generation Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX) |
| Macrocells | 560 | — |
| Flip-Flops | 772 | — |
| User I/Os | 216 | — |
| Dedicated Inputs | 12 | — |
| Logic Elements / Gates | 12,000 usable gates | — |
| Internal Frequency (fMAX) | 145 MHz | — |
| Propagation Delay (tPD) | 11.4 ns | — |
| Clock-to-Output (tCO) | 16.6 ns | — |
| Supply Voltage (VCCINT/VCCIO) | 4.5 V to 5.5 V (3.3 V or 5 V I/O) | 5.0 V |
| In-System Programmability | 5.0-V ISP via JTAG | — |
| Boîtier | 280-pin PGA (ceramic, metal-sealed cofired) | — |
| Température de fonctionnement | -40 °C to 85 °C (industrial) | — |
| Process Technology | CMOS EEPROM | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic CPGA, contains lead) |
| Niveau de sensibilité à l'humidité (MSL) | MSL-3 (168 hours) | — |
| Family | — | MAX 9000 |
| Device Type | — | EE PLD (CMOS EEPROM-based CPLD) |
| Macro Cells | — | 560 |
| Typical Gates | — | 12,000 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Propagation Delay (tpd) | — | 15 ns (speed grade -15) |
| Propagation Delay (alternate datasheet figure) | — | 16.6 ns |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Package Type | — | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Type de montage | — | Through-Hole |
| Programmability | — | In-System Programmable (ISP) via JTAG IEEE 1149.1 |
| Technology | — | CMOS EEPROM, 0.5 um process (MAX third-gen) |
| Statut du cycle de vie | — | Obsolete (legacy Altera MAX 9000 family) |