EPM9560GI280-15 vs EPM9560GC280-15 对比

详细并排对比 EPM9560GI280-15 出自 Intel 和 EPM9560GC280-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM9560GI280-15 EPM9560GC280-15
品牌 Intel Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $110.00 $115.00
Device Family MAX 9000 —
Architecture CMOS EEPROM, third-generation Multiple Array MatriX (MAX) Multiple Array MatriX (MAX)
Macrocells 560 —
Flip-Flops 772 —
User I/Os 216 —
Dedicated Inputs 12 —
Logic Elements / Gates 12,000 usable gates —
Internal Frequency (fMAX) 145 MHz —
Propagation Delay (tPD) 11.4 ns —
Clock-to-Output (tCO) 16.6 ns —
Supply Voltage (VCCINT/VCCIO) 4.5 V to 5.5 V (3.3 V or 5 V I/O) 5.0 V
In-System Programmability 5.0-V ISP via JTAG —
封装 280-pin PGA (ceramic, metal-sealed cofired) —
工作温度 -40 °C to 85 °C (industrial) —
Process Technology CMOS EEPROM —
RoHS 状态 [DATA_NEEDED: RoHS status] Non-compliant (ceramic CPGA, contains lead)
湿敏等级(MSL) MSL-3 (168 hours) —
Family — MAX 9000
Device Type — EE PLD (CMOS EEPROM-based CPLD)
Macro Cells — 560
Typical Gates — 12,000
Maximum Operating Frequency — 117.6 MHz
Propagation Delay (tpd) — 15 ns (speed grade -15)
Propagation Delay (alternate datasheet figure) — 16.6 ns
Operating Temperature (Commercial) — 0C to +70C
Package Type — CPGA-280 (Ceramic Pin Grid Array, 280 pins)
安装类型 — Through-Hole
Programmability — In-System Programmable (ISP) via JTAG IEEE 1149.1
Technology — CMOS EEPROM, 0.5 um process (MAX third-gen)
生命周期状态 — Obsolete (legacy Altera MAX 9000 family)

数据手册与资源

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