EPM9560GI280-15 vs EPM9560GC280-15 Comparison

Detailed side-by-side comparison of EPM9560GI280-15 by Intel and EPM9560GC280-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560GI280-15 EPM9560GC280-15
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status NRND Obsolete
Device Family MAX 9000 —
Architecture CMOS EEPROM, third-generation Multiple Array MatriX (MAX) Multiple Array MatriX (MAX)
Macrocells 560 —
Flip-Flops 772 —
User I/Os 216 —
Dedicated Inputs 12 —
Logic Elements / Gates 12,000 usable gates —
Internal Frequency (fMAX) 145 MHz —
Propagation Delay (tPD) 11.4 ns —
Clock-to-Output (tCO) 16.6 ns —
Supply Voltage (VCCINT/VCCIO) 4.5 V to 5.5 V (3.3 V or 5 V I/O) 5.0 V
In-System Programmability 5.0-V ISP via JTAG —
Package 280-pin PGA (ceramic, metal-sealed cofired) —
Operating Temperature -40 °C to 85 °C (industrial) —
Process Technology CMOS EEPROM —
RoHS Status [DATA_NEEDED: RoHS status] Non-compliant (ceramic CPGA, contains lead)
Moisture Sensitivity Level (MSL) MSL-3 (168 hours) —
Family — MAX 9000
Device Type — EE PLD (CMOS EEPROM-based CPLD)
Macro Cells — 560
Typical Gates — 12,000
Maximum Operating Frequency — 117.6 MHz
Propagation Delay (tpd) — 15 ns (speed grade -15)
Propagation Delay (alternate datasheet figure) — 16.6 ns
Operating Temperature (Commercial) — 0C to +70C
Package Type — CPGA-280 (Ceramic Pin Grid Array, 280 pins)
Mounting Type — Through-Hole
Programmability — In-System Programmable (ISP) via JTAG IEEE 1149.1
Technology — CMOS EEPROM, 0.5 um process (MAX third-gen)
Lifecycle Status — Obsolete (legacy Altera MAX 9000 family)

Datasheets & Resources

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