EPM9560RC240-15C vs EPM9560RC240-15N Comparaison
Comparaison détaillée côte à côte de EPM9560RC240-15C par Intel et EPM9560RC240-15N par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | EPM9560RC240-15C | EPM9560RC240-15N |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | NRND |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $27,85 |
| Family | MAX 9000 | MAX 9000 (third-generation Multiple Array MatriX) |
| Device Type | EEPROM-based CPLD | — |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | 560 |
| Logic Array Blocks | 20 | — |
| User I/O Pins | 187 | — |
| Maximum Internal Frequency | 117.6 MHz | — |
| Propagation Delay (tPD) | 15 ns | — |
| Tension d'alimentation | 5.0 V | 5.0 V |
| Operating Voltage Range | 3.3 V or 5 V | — |
| Boîtier | 240-pin RQFP (PowerQuad II) | RQFP-240 (240-pin Plastic Quad Flat Pack) |
| Terminal Pitch | 0.5 mm | — |
| Type de montage | Surface Mount | Surface Mount |
| Température de fonctionnement | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Configuration Technology | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (ISP via JTAG) | — |
| JTAG Interface | IEEE 1149.1 boundary-scan | — |
| Process Technology | CMOS | — |
| Statut RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance - older Altera RQFP part] |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Series | — | MAX 9000 |
| Logic Array Blocks (LABs) | — | 35 |
| Maximum User I/O Pins | — | 216 |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Internal Counter Frequency (fCNT) | — | 145 MHz |
| Global Setup Time (tFSU) | — | [DATA_NEEDED: tFSU for -15 grade] |
| Clock-to-Output Time (tFCO) | — | [DATA_NEEDED: tFCO for -15 grade] |
| Logic Family | — | CMOS (EEPROM-based) |
| Programmability | — | In-system programmable (IEEE 1532/JTAG) |
| Boundary-Scan Test | — | JTAG (IEEE 1149.1) |