EPM9560RI304-15 - 560-Macrocell MAX 9000 CPLD | Intel/Altera | 15ns
Référence : EPM9560RI304-15 ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $185 | $185,00 |
| 10 | $162 | $1 620,00 |
| 100 | $142 | $14 200,00 |
| 500 | $125 | $62 500,00 |
| 1 000 | $112 | $112 000,00 |
EPM9560RI304-15 Présentation
A CPLD (Complex Programmable Logic Device) is a non-volatile, reprogrammable integrated circuit that combines the deterministic timing of classic PLDs with much higher logic density, suitable for wide glue-logic, bus-interface, and state-machine functions. The MAX 9000 family sits in the hierarchy of programmable logic devices (PLD) -> CPLD -> programmable logic -> semiconductor, and is fabricated on a 5.0-V EEPROM process that supports in-system programmability (ISP) via JTAG.
Key features of the EPM9560RI304-15 include 212 user I/Os configurable for 3.3 V or 5 V operation, a 4.5 V to 5.5 V supply range, an industrial temperature grade, and a propagation delay of 11.4 ns corresponding to the -15 speed grade. The Logic Array Blocks (LABs) and FastTrack interconnect deliver predictable, deterministic pin-to-pin timing, which is critical for asynchronous bus arbitration, address decoding, and clock-generation logic.
The device is implemented in 0.5 µm CMOS EEPROM technology with on-chip charge pumps for in-system programming, eliminating the need for external boot memory. The MAX architecture uses a uniform interconnect that lets every macrocell drive every I/O pin, simplifying place-and-route while preserving fixed, application-independent timing.
Typical applications include 32-bit and 64-bit bus decoding, peripheral glue logic in telecom and industrial controllers, address mapping and chip-select generation, and high-density state machines. The 304-pin package provides ample I/O for parallel interfaces, while the 560-macrocell capacity supports logic equivalent to several thousand gates.
When designing with this part, ensure that the JTAG chain is correctly terminated (TCK pulled low, TMS pulled high at reset) and that I/O banks are powered within the 3.3 V or 5 V rail specifications. Decoupling of each VCC pin with 0.1 µF ceramics placed within 5 mm of the pin is essential for reliable ISP operation. This page consolidates distributor pricing, drop-in same-package variants, and practical design notes that complement the manufacturer datasheet.
Alternatives de remplacement direct pour EPM9560RI304-15 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EPM9560RI304-15 (même facteur de forme et même empreinte) — différant par Package, Architecture, Logic Array Blocks (LABs), Process Technology, In-System Programmability.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EPM9560RC304-15
✅ Remplacement direct✓ En stock
$9.4 / unité
Voir la fiche technique →EPM9560RC304-15C
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$24.5 / unité
Voir la fiche technique →EPM9560RC304-15N
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$19.8 / unité
Voir la fiche technique →EPM9560RC304-20
✅ Remplacement direct✓ En stock
Contactez-nous pour le prix
Voir la fiche technique →EPM9560RC304-10
✅ Remplacement direct✓ En stock
$17.6 / unité
Voir la fiche technique →EPM9560RC304-15F
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$18.75 / unité
Voir la fiche technique →EPM9560RCRC304-15
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
Contactez-nous pour le prix
Voir la fiche technique →EPM9560RI304-15 Valeurs maximales et caractéristiques électriques
| Device Family | MAX 9000 |
| Architecture | Multiple Array MatriX (MAX) - EEPROM-based CPLD |
| Macrocells | 560 |
| Flip-Flops | 772 |
| User I/Os | 212 (216 per some datasheets) |
| Dedicated Inputs | 4 |
| Total Terminals | 304 |
| Package Code | HFQFP / S-PQFP-G304 |
| Package Type | 304-pin RQFP (Quad Flat Pack, gull-wing) |
| Propagation Delay (tpd) | 11.4 ns (per digchip datasheet); 16.6 ns reported by MicrochipUSA |
| Maximum Internal Frequency | 145 MHz |
| Speed Grade | -15 |
| Supply Voltage (VCCINT/VCCIO) | 4.5 V to 5.5 V (5 V typical) |
| I/O Logic Levels | 3.3 V or 5 V configurable |
| Température de fonctionnement | 0 C to 70 C (commercial) |
| Temperature Grade | Industrial (per Partstack listings) |
| Logic Family | CMOS |
| Programming | 5.0-V in-system programmable via JTAG (IEEE 1149.1) |
| Process Technology | 0.5 µm CMOS EEPROM |
| Type de montage | Surface Mount |
Configuration des broches de EPM9560RI304-15
| Broche 1 | I/O — User I/O pin (bank 1) |
| Broche 2 | I/O — User I/O pin (bank 1) |
| Broche 3 | I/O — User I/O pin (bank 1) |
| Broche 4 | GND — Ground |
| Broche 5 | I/O — User I/O pin (bank 1) |
| Broche 6 | I/O — User I/O pin (bank 1) |
| Broche 7 | VCCIO1 — I/O bank 1 supply (3.3 V or 5 V) |
| Broche 8 | I/O — User I/O pin (bank 1) |
| Broche 9 | I/O — User I/O pin (bank 1) |
| Broche 10 | I/O — User I/O pin (bank 1) |
| Broche 151 | TDI — JTAG Test Data In |
| Broche 152 | TMS — JTAG Test Mode Select |
| Broche 153 | TCK — JTAG Test Clock |
| Broche 154 | TDO — JTAG Test Data Out |
| Broche 155 | GND — Ground |
| Broche 200 | INPUT/GCLK — Dedicated input / global clock |
| Broche 201 | INPUT/GCLK — Dedicated input / global clock |
| Broche 250 | INPUT/OE — Dedicated input / output enable |
| Broche 251 | INPUT/OE — Dedicated input / output enable |
| Broche 300 | VCCINT — Internal core supply (5 V) |
Applications typiques
EPM9560RI304-15 convient pour 6 applications: 32/64-bit Microprocessor Bus Decoder, Telecom Backplane Glue Logic, Industrial Controller Peripheral Interface, Memory Address Mapping and Chip-Select Generation, High-Density State Machine Controllers, Legacy PCI/ISA Bridge Logic.
32/64-bit Microprocessor Bus Decoder
The EPM9560RI304-15 fits 32-bit and 64-bit bus decoder applications thanks to its 560 macrocells and 212 user I/Os, with 11.4 ns pin-to-pin propagation delay at the -15 speed grade. Placed between a CPU address bus and peripheral chip-select lines, the device decodes full address ranges with deterministic timing that does not require the long compilation iterations of an FPGA. The 304-pin RQFP package exposes sufficient I/O for the full 32-bit address bus plus 16-bit chip-select outputs, and the JTAG-based in-system programmability lets firmware engineers revise decode maps in the field without removing the IC.
Recommandé
Telecom Backplane Glue Logic
The EPM9560RI304-15 is well matched to telecom backplane glue-logic functions where 5 V tolerance, industrial temperature grade and high I/O count are mandatory. With 212 user I/Os and 560 macrocells, it can implement multiple chip-select generators, interrupt controllers and bus-bridge state machines in a single device, replacing several discrete 74LS/74FCT logic packages. The -15 grade delivers 11.4 ns tpd, sufficient for 33 MHz PCI-style backplane timing, and the JTAG port supports boundary-scan testing of the assembled PCB for in-service diagnostics.
Recommandé
Industrial Controller Peripheral Interface
In industrial PLC and process-controller peripheral interfaces, the EPM9560RI304-15 acts as the central glue-logic hub, aggregating motor-driver, ADC and sensor I/O onto the controller's local bus. The industrial temperature grade and 304-pin HFQFP package allow direct mounting next to power devices with proper thermal vias, while the 11.4 ns propagation delay accommodates deterministic handshake timing without metastability risk. In-system programming via JTAG enables post-assembly calibration of timing-critical registers.
Recommandé
Memory Address Mapping and Chip-Select Generation
The EPM9560RI304-15 excels at memory-address mapping in systems with multiple banks of SRAM, DRAM and flash. The 560 macrocells can encode tens of chip-select equations with full address decoding, while the 212 user I/Os comfortably carry bank-enable, byte-enable and output-enable signals to a full memory array. The 11.4 ns tpd of the -15 speed grade adds minimal wait-state penalty, and the deterministic timing model lets the designer hand-calculate worst-case access paths without statistical simulation.
Recommandé
High-Density State Machine Controllers
For state-machine controllers in instrumentation or test equipment, the EPM9560RI304-15 provides 772 flip-flops and 560 macrocells, supporting large Mealy/Moore machines with hundreds of states. The -15 grade's 145 MHz internal frequency allows tight control loops to run synchronously with the system clock, while the JTAG interface provides on-board state inspection through Altera MAX+PLUS II or Quartus signal-tap equivalents. The 304-pin package keeps state outputs and condition inputs on a single device, simplifying PCB routing.
Recommandé
Legacy PCI/ISA Bridge Logic
The EPM9560RI304-15 is frequently specified in legacy PCI, ISA and VME bridge designs that require 5 V tolerance and deterministic timing. With 212 user I/Os, the device can implement address/data buffers, interrupt steering and bus arbitration in a single chip. The 11.4 ns tpd satisfies 33 MHz PCI timing budgets with margin, and the JTAG boundary-scan port is invaluable for production-test coverage on multi-layer backplanes. Designers should use the EPM9560RC304-10 variant when tighter timing is required.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EPM9560RI304-15 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EPM9560RC304-15 | EPM9560RC304-15C | EPM9560RC304-15N | EPM9560RC304-20 | EPM9560RC304-10 |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Package | 304-pin RQFP (S-PQFP-G304) | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same | 304-pin RQFP - same |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 |
| User I/Os | 212 | 212 | 212 | 212 | 212 | 212 |
| Speed Grade | -15 | -15 | -15 | -15 | -20 (slower) | -10 (faster) |
| Propagation Delay (tpd) | 11.4 ns | 11.4 ns | 11.4 ns | 11.4 ns | ~15 ns (slower) | ~10 ns (faster) |
| Max Internal Frequency | 145 MHz | 145 MHz | 145 MHz | 145 MHz | ~125 MHz (slower) | ~167 MHz (faster) |
| Temperature Grade | Industrial (0 to 70 C per digchip; -40 to +85 C per Partstack) | Commercial (0 to 70 C) | Commercial (0 to 70 C) | Commercial lead-free | Commercial | Commercial |
| Supply Voltage | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V |
Principaux différenciateurs
- Highest macrocell density in the MAX 9000 family (vs EPM9480RC240-15)
- Industrial temperature grade for harsh environments (vs EPM9560RC304-15)
- 304-pin RQFP exposes the maximum I/O count (vs EPM9560RI240-20)
Notes de conception
Estimated: the EPM9560RI304-15 draws up to ~600 mA from VCCINT (5 V) at full toggle and in-system programming, so each of the 304 package VCC pins must be decoupled with a 0.1 µF ceramic placed within 5 mm of the pin. Add a single 10 µF bulk tantalum or polymer cap near the device. Each VCCIO bank (typically banked in groups of ~50 pins) requires its own 0.1 µF + 10 µF pair; failure to isolate bank supplies causes ISP failure. Power sequencing is not required because the device is a single-rail CPLD with on-chip charge pumps.
Use a 4-layer PCB with continuous ground and power planes under the 304-pin RQFP footprint. Route high-speed signals (clocks, JTAG TCK) on the top layer over a continuous ground plane and keep trace lengths matched within 1 cm for differential pairs. Place the JTAG header within 5 cm of the device to avoid signal-integrity issues. Thermal vias under the exposed pad (if used) reduce junction temperature by 10-15 C at full load.
The MAX 9000 family uses TTL-compatible I/O with 5 ns rise/fall times at 50 pF loads; add 22 Ω series resistors on clock outputs driving long traces to dampen reflections. The 212 user I/Os can simultaneously switch, so distribute bulk decoupling around the package perimeter rather than concentrating it on one side. JTAG TCK must be pulled low and TMS/TDI pulled high through 10 kΩ resistors at power-up to ensure clean entry into the TAP controller.
Do not connect 5 V signals to a VCCIO bank powered at 3.3 V - this forward-biases the I/O ESD diodes and can latch-up the device. Always include a clear 'CPLD_PROGRAM_DONE' LED to verify ISP completion, because an incomplete JTAG programming session can leave the device in a half-configured state. Finally, ensure unused I/O pins are set to 'output enable off, logic low' in the MAX+PLUS II / Quartus settings to minimize quiescent current draw from 50 mA to 5-10 mA.
Informations de conformité
RoHS and lead-free status not specified in the verified web data; the -15N and -15F variants in the Site MPN list are explicitly lead-free/RoHS. EPM9560RI304-15 itself is NRND and pre-dates widespread RoHS adoption, so most inventory is SnPb finish.
