K3K8K80BM-MGCP vs K3K9K90BM-MGCP Comparaison
Comparaison détaillée côte à côte de K3K8K80BM-MGCP par Samsung Electronics et K3K9K90BM-MGCP par Samsung Electronics. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | K3K8K80BM-MGCP | K3K9K90BM-MGCP |
|---|---|---|
| Marque | Samsung Electronics | Samsung Electronics |
| Catégorie | Memory ICs | Memory ICs |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $0,00 | $47,15 |
| Type de mémoire | LPDDR5 SDRAM (DRAM) | LPDDR5 SDRAM (CMOS) |
| Density | 64 Gb | — |
| Organisation de la mémoire | 2G x 32 | [DATA_NEEDED: density and organization] |
| Débit de données | 6400 Mbps | — |
| Interface | LPDDR5 (CMOS) | — |
| Boîtier | FBGA-315 (PBGA315) | PBGA (Plastic Ball Grid Array) |
| Supply Voltages | 500 mV, 900 mV, 1.05 V, 1.8 V | — |
| Température de fonctionnement | -25C to +85C | [DATA_NEEDED: operating temperature range] |
| Type de montage | Surface Mount | Surface Mount |
| Technology | CMOS | — |
| Memory Category | Volatile DRAM | — |
| Statut RoHS | Compliant | [DATA_NEEDED: RoHS status] |
| Lead Free | Yes | — |
| Application Class | Specialized ICs / Memory | — |
| I/O Width | 32-bit | — |
| Pin Speed | — | Up to 6400 Mbps (family maximum per Samsung LPDDR5 page) |
| Interface Width | — | x32 (family standard for K3K/K3L BM packages) |
| Ball Count | — | [DATA_NEEDED: ball count] |
| Supply Voltage (VDD) | — | [DATA_NEEDED: VDD voltage] |
| Refresh | — | Self-refresh with per-bank refresh support (LPDDR5 standard) |
| Power Saving vs LPDDR4X | — | Approximately 20% (Samsung published figure) |
| Max Bandwidth | — | Up to 51.2 GB/s (family maximum per Samsung LPDDR5 page) |
| Moisture Sensitivity Level | — | [DATA_NEEDED: MSL level] |
| Clocking | — | WCK (word clock) architecture |
| Standards | — | JEDEC LPDDR5 |