RTAX250SL-CG624E vs RTAX250S-CG624E Comparaison
Comparaison détaillée côte à côte de RTAX250SL-CG624E par Microchip Technology et RTAX250S-CG624E par Microchip Technology. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Microchip Technology
RTAX250SL-CG624E - 250K-Gate Rad-Tolerant FPGA | Microchip
RTAX250SL-CG624E ✓ ActifMicrochip Technology
RTAX250S-CG624E - 250K-Gate Rad-Tolerant FPGA | Microchip
RTAX250S-CG624E ✓ ActifComparaison des spécifications
| Paramètre | RTAX250SL-CG624E | RTAX250S-CG624E |
|---|---|---|
| Marque | Microchip Technology | Microchip Technology |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Actif |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $1 375,00 | $0,00 |
| Family | RTAX-S/SL Radiation-Tolerant FPGA | RTAX-S radiation-tolerant FPGA |
| System Gates | 250000 | 250000 gates |
| Logic Cells (CLBs) | 2816 | 2816 |
| Maximum Frequency | 649 MHz | — |
| Process Technology | 0.15 um CMOS | 0.15 um CMOS |
| Core Supply Voltage | 1.5 V | 1.5 V |
| Supply Voltage Tolerance | +/-0.15 V | — |
| Maximum Combinatorial Delay | 0.93 ns | — |
| Boîtier | 624-Pin CCGA (Ceramic Column Grid Array) | — |
| Température de fonctionnement | -55C to +125C | -55C to +125C |
| Logic Family | CMOS | CMOS |
| Radiation Tolerance | SEU-hardened registers; SEU rate < 10-10 errors/bit-day | — |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | — |
| Clocking | Segmentable clocks, chip-wide highway routing | — |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS status] | — |
| Programmability | Live at power-up, true single-chip | — |
| Maximum Toggle Frequency | — | 649 MHz |
| CLB Combinatorial Delay (max) | — | 0.930 ns |
| Package Type | — | CCGA-624 (ceramic column grid array, 624 pins) |
| Programming Technology | — | Antifuse (one-time programmable) |
| SEU Hardening | — | SEU-hardened registers, no external TMR required |
| SEU Immunity | — | Immune to single-event upsets to specified LET threshold; SEU rate < 10-10 errors/bit-day |
| Power-Up Behavior | — | Live at power-up (true single-chip) |
| Target Application | — | Space-flight systems |