XC3090L-8TQG176C vs XC3090L-6TQG176C Comparaison
Comparaison détaillée côte à côte de XC3090L-8TQG176C par Xilinx et XC3090L-6TQG176C par Xilinx. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Xilinx
XC3090L-8TQG176C - 320 CLB FPGA, 6K Gates, 80MHz, TQFP-176 | Xilinx
XC3090L-8TQG176C Obsolete
Comparaison des spécifications
| Paramètre | XC3090L-8TQG176C | XC3090L-6TQG176C |
|---|---|---|
| Marque | Xilinx | Xilinx |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $28,75 | $63,00 |
| Family | XC3000L Logic Cell Array | XC3000L Low-Voltage Logic Cell Array |
| Logic Cell Count (CLBs) | 320 | — |
| Equivalent Gates | 5,000 (6,000 max usable) | — |
| Supply Voltage (VCC) | 3.3 V | — |
| Maximum Operating Frequency | 80 MHz | — |
| Speed Grade | -8 | -6 (6 ns tpd) |
| Boîtier | TQFP-176 (TQG176) | TQG176 (Thin Quad Gull-Wing, 176 pins) |
| Process Technology | CMOS, low-voltage | — |
| Configuration Memory | Internal SRAM (reprogrammable) | SRAM (volatile, in-system programmable) |
| Configuration Modes | Serial, peripheral, master/slave parallel | — |
| I/O Standard | TTL-compatible | — |
| Température de fonctionnement | Commercial (0C to +85C) | Commercial (0C to +70C) |
| Nombre de broches | 176 | — |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS compliance] | unknown (legacy family, pre-dates RoHS documentation conventions) |
| Series | — | XC3000L |
| Device | — | XC3090L |
| User I/O Count | — | 138 |
| Tension d'alimentation | — | 3.3 V |
| Combinatorial Logic Delay (tpd) | — | 6 ns |
| Family Differentiator | — | Low-voltage 3.3V core vs 5.0V XC3000A |
| Compatible Programming Tools | — | Xilinx XChecker, JTAG boundary-scan, PROM-based serial configuration |
| Lead Free | — | unknown |
| Pinout Type | — | Perimeter I/O ring with user I/O and dedicated configuration pins |