XC3090LTM-100PC84C vs XC3090L-8PCG84C Comparaison
Comparaison détaillée côte à côte de XC3090LTM-100PC84C par Xilinx et XC3090L-8PCG84C par Xilinx. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | XC3090LTM-100PC84C | XC3090L-8PCG84C |
|---|---|---|
| Marque | Xilinx | Xilinx |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Obsolete | Dernier achat |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $41,40 | $26,10 |
| Manufacturer | Xilinx | — |
| Series | XC3000L Logic Cell Array Family | — |
| Family | XC3090 | XC3000A/L Series FPGA |
| Logic Cells / CLBs | 320 Configurable Logic Blocks | 70 Configurable Logic Blocks |
| Typical Gate Count | 5,000 to 6,000 gates | — |
| Technology | 5V CMOS, SRAM-based configuration | — |
| Performance Grade | 100 MHz | — |
| Boîtier | 84-pin PLCC (PC84) | 84-pin PLCC (J-Lead, PCG84) |
| Terminal Form | J-Lead (Surface Mount) | — |
| Package Code | QCCJ (Plastic Leaded Chip Carrier) | — |
| Operating Temperature Grade | Commercial | — |
| Configuration Memory | SRAM (volatile, requires external bitstream) | — |
| I/O Standard | 5V CMOS / TTL compatible | — |
| Programming Method | External configuration PROM or microcontroller bitstream load | — |
| Statut RoHS | [DATA_NEEDED: legacy device, pre-RoHS era] | unknown |
| Statut du cycle de vie | Obsolete / Discontinued by manufacturer | — |
| Gate Count | — | 6,400 gates (typical) |
| Configuration Program Store | — | 64,160 bits |
| User I/O Pins | — | 70 (maximum) |
| Supply Voltage (VCC) | — | 3.0 V to 3.6 V (low-voltage 'L' variant) |
| Speed Grade | — | -8 (moderate) |
| Température de fonctionnement | — | 0 C to +70 C (commercial 'C' suffix) |
| Configuration Modes | — | Serial master/slave, parallel master/slave, peripheral mode |
| Process Technology | — | [DATA_NEEDED: process node] |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |
| Configuration Clock Range | — | [DATA_NEEDED: CCLK frequency range] |
| Type de montage | — | Surface Mount (PLCC J-Lead) |
| Lead-Free | — | unknown |
| Niveau MSL | — | [DATA_NEEDED: MSL rating] |
| Programming Technology | — | SRAM-based, in-system reconfigurable |