XC6SLX16-2FT256C vs XC6SLX16-2FTG256C Comparaison
Comparaison détaillée côte à côte de XC6SLX16-2FT256C par AMD et XC6SLX16-2FTG256C par AMD. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Comparaison des spécifications
| Paramètre | XC6SLX16-2FT256C | XC6SLX16-2FTG256C |
|---|---|---|
| Marque | AMD | AMD |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | NRND |
| Device Type | FPGA | — |
| FPGA Family | Spartan-6 LX | — |
| Configurable Logic Cells | 14,579 cells | — |
| Configurable Logic Blocks | 1,139 CLBs | — |
| Internal Frequency | 667 MHz | — |
| I/O Count | 186 I/O | — |
| Process Technology | 45 nm CMOS | — |
| Core Supply Voltage | 1.2 V | — |
| Speed Grade | -2 | -2 |
| Temperature Grade | C, commercial | — |
| Température de fonctionnement | 0°C to 85°C | 0 °C to +85 °C (Commercial) |
| Boîtier | 256-LBGA | 256-ball Fine-Pitch Thin BGA (FTG256), 17×17 mm, 1.0 mm pitch |
| Terminal Count | 256 terminals | — |
| Type de montage | Surface Mount | Surface Mount |
| Package Shape | Square | — |
| Terminal Form | Ball | — |
| Lead-Free Status | Lead free | — |
| Statut RoHS | [DATA_NEEDED: RoHS compliance status] | — |
| REACH Status | [DATA_NEEDED: REACH compliance status] | — |
| Block RAM | [DATA_NEEDED: block RAM capacity] | — |
| DSP Resources | [DATA_NEEDED: DSP resource count] | — |
| Family | — | Spartan-6 LX |
| Logic Cells | — | 14,579 |
| Configurable Logic Blocks (CLBs) | — | 1,139 |
| Slices | — | 2,278 |
| Block RAM Bits | — | 589,824 bits |
| Block RAM Blocks (18 Kb) | — | 32 |
| DSP Slices (18×18 multipliers) | — | 32 |
| Maximum User I/Os | — | 186 |
| Maximum Single-Ended I/O Banks | — | 4 |
| Process Node | — | 45 nm CMOS, 9-metal layer |
| Supply Voltage (Core) | — | 1.2 V nominal |
| Lead-Free / RoHS | — | Yes (compliant) |
| Configuration Modes | — | JTAG, SPI (x1/x2/x4), BPI (x8/x16), Slave-Parallel |
| Clock Management Tiles (CMTs) | — | 2 (each with PLL + MMCM) |
| PCIe Support | — | Soft IP only (no integrated PCIe hard cores) |