ADC10662CIWM/NOPB - 10-Bit 1.5 MSPS Dual-Input ADC | TI
Référence : ADC10662CIWM/NOPB ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $12.85 | $12,85 |
| 10 | $11.58 | $115,80 |
| 100 | $9.92 | $992,00 |
| 500 | $8.74 | $4 370,00 |
| 1 000 | $7.81 | $7 810,00 |
ADC10662CIWM/NOPB Présentation
What is a sub-ranging flash ADC? A sub-ranging (or two-step) flash ADC performs coarse conversion with a lower-resolution flash, then a fine conversion with a second flash, effectively partitioning the conversion range to reduce comparator count, power, and input loading. The category hierarchy is: sub-ranging flash ADC -> successive-approximation-flash hybrid ADC -> analog-to-digital converter -> data converter -> signal chain IC -> semiconductor. This architecture is widely used in video, imaging, and instrumentation sub-systems where 8-12 bit resolution and 1-50 MSPS rates must coexist with modest power budgets.
Key features of the ADC10662CIWM/NOPB include two analog input channels selected by the MUX pin, an internal sample-and-hold that holds the sampled input through conversion, a 0 V to 5 V analog input range referenced to a single +5 V supply, and TTL/CMOS-compatible digital outputs. Its 1.5 MSPS throughput supports real-time sampling for DSP front ends and disk-drive read channels, while its low-power CMOS design keeps dissipation low even at the maximum sampling rate.
The device uses a single +5 V analog supply and a separate +5 V digital supply for noise isolation. Built-in reference, clock, and conversion-start logic simplify interface to microcontrollers and DSPs. The on-chip input multiplexer and sample-and-hold make the device well suited for multi-channel data-acquisition systems where PCB area and component count are constrained.
Typical applications include digital signal processor front ends for motor control and instrumentation, disk-drive servo/READ channels, mobile telecommunications baseband conversion, and process-control data-acquisition boards. Designers should note that the pin-compatible ADC10664 (12-bit, same 1.5 MSPS) is available when resolution, not speed, must be increased. The wide 24-SOIC footprint simplifies thermal management compared with small-outline alternatives, and provides robust manufacturing yields.
Alternatives de remplacement direct pour ADC10662CIWM/NOPB — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec ADC10662CIWM/NOPB (même facteur de forme et même empreinte) — différant par Architecture, Package, Analog Supply Voltage, Conversion Time, Input Type.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
ADC10664CIWM/NOPB
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
ADC10062CIWM/NOPB
✅ Remplacement direct✓ En stock
$5.85 / unité
Voir la fiche technique →ADC10158CIN/NOPB
✅ Remplacement direct✓ En stock
$4.74 / unité
Voir la fiche technique →ADC10464CIWMX/NOPB
✅ Remplacement direct✓ En stock
$5.74 / unité
Voir la fiche technique →ADC10662CIWM/NOPB Valeurs maximales et caractéristiques électriques
| Résolution | 10 bits |
| Fréquence d'échantillonnage | 1.5 MSPS (minimum) |
| Conversion Time | 360 ns |
| Number of Inputs | 2 (single-ended, MUX selected) |
| Architecture | Sub-ranging flash (two-step) |
| Analog Supply Voltage | Single +5 V |
| Digital Supply Voltage | Single +5 V |
| Analog Input Range | 0 V to +5 V |
| Power Dissipation | 235 mW (typical) |
| Output Interface | Parallel, TTL/CMOS-compatible |
| Sample-and-Hold | Internal, on-chip |
| On-Chip Reference | Yes (internal) |
| Boîtier | 24-pin SOIC (WM), wide body |
| Type de montage | Surface Mount |
| Statut RoHS | Compliant (NOPB suffix) |
| Lead Finish | Lead-free (NOPB) |
Configuration des broches de ADC10662CIWM/NOPB
| Broche 1 | MUX — Input channel select (logic low = INL, high = INH) |
| Broche 2 | INL — Analog input, channel Low |
| Broche 3 | VA — Analog +5 V supply |
| Broche 4 | GND — Ground (analog) |
| Broche 5 | INH — Analog input, channel High |
| Broche 6 | REF+ — Reference top (internal +5 V ref out / external ref in) |
| Broche 7 | REF- — Reference bottom (ground) |
| Broche 8 | VBIAS — Bias voltage decoupling |
| Broche 9 | DB0 (LSB) — Digital output bit 0 (LSB) |
| Broche 10 | DB1 — Digital output bit 1 |
| Broche 11 | DB2 — Digital output bit 2 |
| Broche 12 | DB3 — Digital output bit 3 |
| Broche 13 | DB4 — Digital output bit 4 |
| Broche 14 | DB5 — Digital output bit 5 |
| Broche 15 | DB6 — Digital output bit 6 |
| Broche 16 | DB7 — Digital output bit 7 |
| Broche 17 | DB8 — Digital output bit 8 |
| Broche 18 | DB9 (MSB) — Digital output bit 9 (MSB) |
| Broche 19 | OE — Output enable (active low) |
| Broche 20 | CLK — Conversion clock input |
| Broche 21 | SHIELD — Ground / shield pin (per datasheet) |
| Broche 22 | VD — Digital +5 V supply |
| Broche 23 | DGND — Digital ground |
| Broche 24 | NC — Not connected (per datasheet pinout) |
Applications typiques
ADC10662CIWM/NOPB convient pour 6 applications: DSP Front-End Data Acquisition, Disk Drive Read Channel, Mobile Telecommunications Baseband, Industrial Instrumentation & Process Control, Portable Test & Measurement, CCD/CIS Imaging Front Ends.
DSP Front-End Data Acquisition
The ADC10662CIWM/NOPB serves as a high-speed digitizer feeding a DSP for real-time signal processing. Its 1.5 MSPS throughput and 10-bit resolution meet typical 8-14 kHz IF sampling needs in motor-control and audio DSP front ends, while the parallel digital bus pairs directly with DSP parallel ports such as the TI TMS320 series. The on-chip sample-and-hold and dual-input MUX remove the need for external track/hold ICs, shrinking the analog front-end BOM in space-constrained motor-control PCBs.
Recommandé
Disk Drive Read Channel
In disk-drive read-channel electronics, the ADC10662CIWM/NOPB digitizes the preamplifier output at the highest sample-rate corner of the channel, where jitter and aperture-time performance matter. Its 360 ns conversion time and sub-ranging flash architecture deliver the deterministic low-jitter sampling required for channel-bit detection, while the 235 mW dissipation stays within the thermal budget of a sealed HDD assembly. The 24-SOIC wide-body package spreads heat and supports standard SMT reflow.
Recommandé
Mobile Telecommunications Baseband
Mobile telecommunications baseband and IF digitizers benefit from the ADC10662CIWM/NOPB's 1.5 MSPS rate and 5 V single-supply operation. It samples at sufficient rate for legacy 2G/early-3G IF chains without oversampling or downconversion, while the parallel TTL/CMOS interface drives ASIC baseband logic directly. The internal sample-and-hold compensates for analog input-bandwidth limitations seen at higher IF frequencies, keeping spurious tones below the baseband signal band.
Recommandé
Industrial Instrumentation & Process Control
For industrial instrumentation data-acquisition boards, the ADC10662CIWM/NOPB pairs its 1.5 MSPS throughput with the dual-input MUX so two transducer channels (e.g., a primary sensor plus reference) can be digitised with one ADC. The 10-bit resolution is appropriate for vibration, temperature, and pressure transducer digitizers where 1 part in 1024 precision (about 0.1 percent) is sufficient. Its industrial-temperature SOIC package meets factory-floor reliability requirements.
Recommandé
Portable Test & Measurement
Battery- and line-powered test instruments leverage the ADC10662CIWM/NOPB's modest 235 mW power dissipation and 5 V supply. The 1.5 MSPS real-time sampling captures transient events in scope and datalogger designs up to 750 kHz analog bandwidth (Nyquist), while the internal sample-and-hold maintains conversion-window timing precision. The 24-SOIC wide-body footprint simplifies hand-prototyping on DIP-to-SOIC adapter boards during lab validation.
Recommandé
CCD/CIS Imaging Front Ends
CCD and CIS imaging front-end boards use the ADC10662CIWM/NOPB to digitize video-rate analog signals at 1.5 MSPS per channel. Two input MUX channels allow pixel-data plus correlated double-sampling on a single ADC, eliminating channel-to-channel gain mismatches. The sub-ranging flash architecture delivers the low aperture jitter required to preserve CCD/CIS noise performance, while the parallel TTL outputs feed FPGA video pipelines directly with no glue logic.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour ADC10662CIWM/NOPB — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | ADC10664CIWM/NOPB | ADC10062CIWM/NOPB | ADC10158CIN/NOPB | ADC10464CIWMX/NOPB |
|---|---|---|---|---|---|
| Package | 24-SOIC (WM) | 24-SOIC (WM) - same | 24-SOIC (WM) - same | 24-SOIC - same | 24-SOIC (WM) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 10 bits | 12 bits | 10 bits | 10 bits | 10 bits |
| Sampling Rate | 1.5 MSPS | 1.5 MSPS | 2.5 MSPS | ~225 KSPS | 500 KSPS |
| Number of Inputs | 2 (MUX) | 2 (MUX) | 2 (MUX) | 8 (MUX) | 2 (MUX) |
| Supply Voltage | +5 V single | +5 V single | +5 V single | +5 V single | +5 V single |
Principaux différenciateurs
- Sub-ranging flash architecture with only 235 mW dissipation (vs ADC10158CIN/NOPB)
- Direct drop-in upgrade path to 12-bit ADC10664 (vs ADC10664CIWM/NOPB)
- 1.5 MSPS in dual-input MUX at this price tier (vs ADC10464CIWMX/NOPB)
Notes de conception
Provide separate analog (VA) and digital (VD) +5 V supplies, even when they originate from the same rail, to prevent digital switching noise coupling into the analog front-end. Decouple VA with a 10 uF tantalum plus 0.1 uF ceramic placed physically adjacent to the VA pin, and replicate the same stack on VD. The datasheet recommends a 0.1 uF ceramic on VBIAS to filter the internal bias-generator node.
Route the analog inputs (INL, INH) over a contiguous ground plane and away from the parallel digital bus DB0-DB9. Use a separate analog ground that ties to a single point near the ADC GA0GND pin, with the digital ground returning to the same star point. This isolates clock-induced digital noise from corrupting the 10-bit conversion. Keep input traces short and impedance-controlled to minimize aperture-jitter sensitivity.
Place the CLK driver within 25 mm of the CLK pin and route over a continuous ground reference; excessive trace length on CLK adds jitter to the conversion-timing aperture. The 24-pin SOIC wide-body footprint has generous pin-to-pin spacing, simplifying manual prototype hand-soldering on adapter boards. Avoid vias in the analog input path; use a top-layer trace from the input BNC or SMA connector directly to the INL/INH pin.
Drive the OE (output enable) line from the system controller with a logic-low-true signal; leaving OE floating allows digital outputs to float during read cycles and may inject bus-noise into adjacent analog traces. The TTL/CMOS-compatible parallel outputs DB0-DB9 sink/source approximately 4 mA, so an external buffer (e.g., 74LVC245) is required when driving heavier loads. Tie unused MUX channel input to mid-scale (2.5 V) via a buffer to reduce channel-to-channel crosstalk.
Do not apply input voltages outside 0 V to +5 V; the ADC10662's analog input stage does not include over-voltage protection and absolute-maximum input exceeds the supply rails will permanently damage the device. Always assert a clean CLK with low jitter; a noisy or stretched clock invalidates the 360 ns conversion timing budget and degrades INL/DNL. When using the internal reference (REF+ pin), connect a 10 uF tantalum plus 0.1 uF ceramic directly on the pin to filter reference noise.
Informations de conformité
NOPB suffix confirms lead-free NiPdAu lead finish and RoHS compliance per TI product marking. Original ADC10662CIWM (without /NOPB) contains lead and is non-RoHS; lifecycle recommends new designs use the /NOPB variant.
