ADC1613S080HN-C18 - 16-bit 80MSPS Single-Channel ADC, JESD204A | Renesas
Référence : ADC1613S080HN-C18 ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $28.5 | $28,50 |
| 10 | $25.2 | $252,00 |
| 100 | $21.75 | $2 175,00 |
| 500 | $18.4 | $9 200,00 |
| 1 000 | $15.95 | $15 950,00 |
ADC1613S080HN-C18 Présentation
An analog-to-digital converter (ADC) is a data-acquisition component that converts a continuous-time, continuous-amplitude analog signal into discrete-time, discrete-amplitude digital words. Pipeline ADCs like the ADC1613S080HN-C18 use a multi-stage switched-capacitor architecture that resolves several bits per clock cycle, achieving high sampling rates with low latency. The ADC sits hierarchically as: pipeline ADC -> data converter -> ADC -> data acquisition IC -> signal chain -> mixed-signal semiconductor.
Differentiating features include a single 1.8 V supply rail for the analog domain, integrated input common-mode buffer, optional dither for SFDR improvement, and a JESD204A subclass-0 compatible serial output that uses a single lane plus synchronization. According to the IDT/Renesas ADC1613S_SER datasheet, the part is offered in speed grades from 65 MSPS to 125 MSPS, and the -C18 suffix denotes the 80 MSPS grade with specific reel-packaging orientation. The device supports both LVDS and DDR-LVDS physical layers.
The architecture is a 16-stage pipelined switched-capacitor core with proprietary calibration that corrects inter-stage gain and offset errors at power-up. Internal references simplify board design by eliminating external reference components, and the integrated clock divider allows flexible clocking. The JESD204A transmitter implements 8b/10b encoding with deterministic latency and K-character handling for frame synchronization, allowing direct connection to FPGAs and ASICs with JESD204A link ports.
Typical applications include high-density communications receivers, software-defined radio, medical ultrasound front-end digitizers, test and measurement instrumentation, and radar or lidar signal acquisition. The 80 MSPS rate and 16-bit resolution suit bandwidths up to approximately 35 MHz, with ENOB around 12-13 bits at Nyquist for cellular base-station observation receivers.
When designing with this device, ensure the analog input network presents a differential drive within the rated common-mode window and that the JESD204A link partner supports subclass-0 framing. The -C18 suffix indicates the part ships in tape-and-reel orientation code 18 (RD pin count orientation per Renesas ordering scheme).
This page synthesizes distributor pricing, drop-in alternatives from the same Renesas/IDT speed-grade family, and practical design notes not found in the manufacturer datasheet alone.
Alternatives de remplacement direct pour ADC1613S080HN-C18 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec ADC1613S080HN-C18 (même facteur de forme et même empreinte) — différant par Package, Input Type, Output Interface, Sample Rate, RoHS Status.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
ADC1613S065HN-C18
✅ Remplacement direct✓ En stock
$25.1 / unité
Voir la fiche technique →ADC1613S105HN-C18
✅ Remplacement direct✓ En stock
$25.9 / unité
Voir la fiche technique →ADC1613S125HN-C18
✅ Remplacement direct✓ En stock
$22.4 / unité
Voir la fiche technique →ADC1213S080HN-C18
✅ Remplacement direct✓ En stock
$9.45 / unité
Voir la fiche technique →ADC1613S080HN-C1
✅ Remplacement direct✓ En stock
$24.95 / unité
Voir la fiche technique →ADC1410S080HN-C18
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
ADC1613S080HN-C18 Valeurs maximales et caractéristiques électriques
| Résolution | 16 bit |
| Sample Rate | 80 MSPS |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Output Interface | Serial JESD204A (subclass 0) |
| Input Type | Differential |
| Supply Voltage - Analog | 1.8 V |
| Supply Voltage - Digital | 1.8 V |
| Température de fonctionnement | -40C to +85C |
| Boîtier | 32-VFQFPN (HVQFN) 5x5 mm |
| Type de montage | Surface Mount |
| Statut RoHS | Compliant |
| Lead-Free | Yes |
| JESD204A Lanes | 1 lane |
Configuration des broches de ADC1613S080HN-C18
| Broche 1 | CLKN — Differential clock input, negative |
| Broche 2 | CLKP — Differential clock input, positive |
| Broche 3 | VA1P8 — Analog 1.8 V supply |
| Broche 4 | GND — Ground |
| Broche 5 | INP — Differential analog input, positive |
| Broche 6 | INN — Differential analog input, negative |
| Broche 7 | VCM — Common-mode voltage output |
| Broche 8 | VA1P8 — Analog 1.8 V supply |
| Broche 9 | GND — Ground |
| Broche 10 | VD1P8 — Digital 1.8 V supply |
| Broche 11 | GND — Ground |
| Broche 12 | PD — Power-down control input |
| Broche 13 | RESET — Reset input |
| Broche 14 | SDIO — SPI data I/O |
| Broche 15 | SCLK — SPI clock |
| Broche 16 | CSB — SPI chip select, active low |
| Broche 17 | SYNCB — JESD204A synchronization request, active low |
| Broche 18 | GND — Ground |
| Broche 19 | VD1P8 — Digital 1.8 V supply |
| Broche 20 | GND — Ground |
| Broche 21 | SYSREF — JESD204A system reference input |
| Broche 22 | OUTP — JESD204A serial lane, positive |
| Broche 23 | OUTN — JESD204A serial lane, negative |
| Broche 24 | VD1P8 — Digital 1.8 V supply |
| Broche 25 | GND — Ground |
| Broche 26 | NC — Not connected (per datasheet) |
| Broche 27 | NC — Not connected (per datasheet) |
| Broche 28 | VA1P8 — Analog 1.8 V supply |
| Broche 29 | GND — Ground |
| Broche 30 | VA1P8 — Analog 1.8 V supply |
| Broche 31 | GND — Ground |
| Broche 32 | GND — Ground |
Applications typiques
ADC1613S080HN-C18 convient pour 6 applications: Communications Receiver Digitization, Medical Ultrasound Front-End, Test and Measurement Instrumentation, Software Defined Radio (SDR), Industrial Radar and Lidar Digitization, Data Acquisition Systems.
Communications Receiver Digitization
The ADC1613S080HN-C18 suits digital-IF and observation-receiver signal chains where 16-bit resolution at 80 MSPS captures a 35 MHz bandwidth cleanly. Its JESD204A subclass-0 output connects directly to FPGAs with integrated transceivers, eliminating parallel CMOS routing that would otherwise fan out across many board layers. The single-lane link reduces pin count and PCB complexity versus LVDS-parallel ADCs, while the 1.8 V supply enables integration with modern FPGA SoCs. ENOB of 12-13 bits at Nyquist provides sufficient dynamic range for cellular base-station receivers monitoring multiple RF carriers.
Recommandé
Medical Ultrasound Front-End
Ultrasound beamformers require multiple synchronized high-resolution ADCs sampling at 40-80 MSPS, and the ADC1613S080HN-C18 fits this requirement with its 16-bit pipeline core and JESD204A serial interface. The deterministic-latency link simplifies per-channel skew alignment across hundreds of transducer channels, while 1.8 V analog supply keeps per-channel power low enough for portable cart-based systems. Differential analog inputs reject common-mode pickup from piezo transducer cables. The wide -40C to +85C operating range supports clinical-environment thermal envelopes.
Recommandé
Test and Measurement Instrumentation
Digital oscilloscopes, spectrum analyzers, and arbitrary waveform digitizers benefit from the ADC1613S080HN-C18's 16-bit dynamic range at 80 MSPS. The pipelined core with internal calibration provides low INL and DNL for accurate amplitude measurements, while the JESD204A interface streams data to FPGA-based DSP blocks for FFT and trigger processing. Engineers can scale to higher sample rates via the 105 MSPS or 125 MSPS speed grades (ADC1613S105HN-C18, ADC1613S125HN-C18) without redesigning the board footprint.
Recommandé
Software Defined Radio (SDR)
SDR platforms digitize RF signals directly at IF or near-baseband, requiring ADCs with high SFDR and flexible sample rates. The ADC1613S080HN-C18 delivers 16-bit resolution at 80 MSPS, supporting bandwidths of approximately 35 MHz for narrow-band communications and spectrum monitoring. Its JESD204A subclass-0 link enables deterministic latency for time-sensitive protocols like TETRA and DMR. The single 1.8 V supply and low power dissipation suit battery-powered tactical SDRs and software-defined cellular handsets.
Recommandé
Industrial Radar and Lidar Digitization
Automotive and industrial radar front-ends, plus lidar time-of-flight receivers, need wide dynamic range to detect both close-range strong returns and far-range weak returns. The ADC1613S080HN-C18's 16-bit resolution preserves this dynamic range at 80 MSPS, supporting chirp bandwidths up to about 35 MHz. The JESD204A interface transports data directly to FPGA processors that perform range-Doppler FFTs and target classification. The AEC-style operating temperature grade suits industrial environments.
Recommandé
Data Acquisition Systems
Multi-channel data acquisition cards for industrial process control and scientific instrumentation use the ADC1613S080HN-C18 to digitize sensor outputs with 16-bit precision. Its JESD204A serial interface enables high channel density on PCI-Express and PXIe digitizer boards by minimizing FPGA pin consumption. The 80 MSPS rate oversamples most industrial signals, allowing digital filtering for improved effective resolution. Differential inputs reject common-mode noise from industrial cabling and motor drives.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour ADC1613S080HN-C18 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | ADC1613S065HN-C18 | ADC1613S105HN-C18 | ADC1613S125HN-C18 | ADC1213S080HN-C18 | ADC1613S080HN-C1 |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 32-VFQFPN (HVQFN) 5x5 mm | 32-VFQFPN (HVQFN) 5x5 mm - same | 32-VFQFPN (HVQFN) 5x5 mm - same | 32-VFQFPN (HVQFN) 5x5 mm - same | 32-VFQFPN (HVQFN) 5x5 mm - same | 32-VFQFPN (HVQFN) 5x5 mm - same |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 12 bit | 16 bit |
| Sample Rate | 80 MSPS | 65 MSPS | 105 MSPS | 125 MSPS | 80 MSPS | 80 MSPS |
| Number of Channels | 1 | 1 | 1 | 1 | 1 | 1 |
| Output Interface | JESD204A subclass 0 | JESD204A subclass 0 | JESD204A subclass 0 | JESD204A subclass 0 | JESD204A subclass 0 | JESD204A subclass 0 |
| Supply Voltage | 1.8 V analog + 1.8 V digital | 1.8 V + 1.8 V | 1.8 V + 1.8 V | 1.8 V + 1.8 V | 1.8 V + 1.8 V | 1.8 V + 1.8 V |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Principaux différenciateurs
- Single-lane JESD204A output at 80 MSPS (vs ADC1613S125HN-C18)
- Higher dynamic range than 12-bit family member (vs ADC1213S080HN-C18)
- Drop-in speed-grade flexibility (vs ADC1613S065HN-C18)
Notes de conception
Route the differential analog inputs (INP/INN) and differential clock (CLKP/CLKN) as 100-ohm differential pairs with length matching within 0.5 mm. Place the ADC1613S080HN-C18 on a separate analog ground island that joins the digital ground at a single point near the ADC ground pins. Use split-ground planes rather than cut-outs to maintain a low-impedance return path. The JESD204A serial lane (OUTP/OUTN) requires 100-ohm differential routing with controlled 50-ohm characteristic impedance to the FPGA, with length matching to within 0.1 mm.
Power the ADC1613S080HN-C18 from low-noise LDO regulators rather than switching converters, as any supply ripple couples directly into the analog input and degrades SFDR. Place 10 uF ceramic plus 0.1 uF ceramic decoupling capacitors within 5 mm of each VA1P8 and VD1P8 pin. The exposed thermal pad must be soldered to a continuous ground pour with multiple vias for thermal dissipation, especially when operating at 125 MSPS grade variants where power dissipation increases.
Common pitfalls with JESD204A ADCs include mismatched serial lane length causing inter-symbol recovery errors, missing SYSREF signal which prevents deterministic-latency link establishment, and insufficient SPI pull-ups on CSB which causes communication failures. Always verify the JESD204A link-partner FPGA supports subclass 0 deterministic latency before committing to this ADC family. The internal calibration routine requires the RESET pin to be toggled after power-up stabilization, with a 10 ms delay before SPI access.
Informations de conformité
RoHS compliance and lead-free status confirmed via Renesas product page. AEC-Q100 not qualified; this part is not intended for automotive applications. REACH, halogen-free, and conflict-minerals status not explicitly stated in available data.
