ADC1613S125HN-C18 - 16-Bit 125 MSPS Single-Channel ADC | Renesas
MPN: ADC1613S125HN-C18 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.45 | $324.50 |
| 100 | $27.8 | $2,780.00 |
| 500 | $24.15 | $12,075.00 |
| 1,000 | $22.4 | $22,400.00 |
ADC1613S125HN-C18 Overview
This ADC belongs to the pipelined ADC family, which is the dominant converter architecture for high-speed signal capture in communications, radar, and instrumentation. Pipelined ADCs digitize an input signal by cascading low-resolution stage ADCs with residue amplifiers and DACs, achieving high sample rates while maintaining 14-16 bits of resolution with low latency between convert and output. Pipelined ADCs sit hierarchically under high-speed ADC -> data converter -> signal chain IC -> semiconductor, and they typically outperform successive-approximation-register (SAR) ADCs beyond about 10 MSPS.
Key features include a 16-bit output word, a differential analog input, a separate analog and digital supply for noise isolation, an internal reference option with external override capability, and dithering for improved SFDR at small input signals. The JESD204A interface reduces board routing complexity by serializing the data onto a single LVDS pair, but it requires a JESD204A-compliant FPGA or ASIC receiver to deserialize the data into sample-aligned words.
Technically, the ADC1613S125HN-C18 uses multi-stage switched-capacitor pipeline stages clocked by an internal PLL, with digital error correction in the final stage. Its reported SNR performance rivals Sigma-Delta converters of similar bandwidth while its power consumption remains moderate for a 125 MSPS 16-bit pipelined part. The HVQFN-32 package provides a low thermal resistance path so the device can sustain high sample rates without thermal throttling.
Typical applications include multi-carrier GSM/EDGE/WCDMA/LTE base-station receivers, radar digitizers, medical imaging front-ends, cable modem downstream capture, and high-end test and measurement equipment. The combination of 16-bit resolution, 125 MSPS sampling, and JESD204A serial output makes it suited to systems requiring high dynamic range over wide IF bandwidths.
When designing with this part, verify that the host FPGA supports JESD204A (not only JESD204B/C) before prototyping, and ensure the JESD204A subclass 0 deterministic latency requirements are met by sharing the device clock between ADC and FPGA. The exposed thermal pad must be soldered to a continuous ground copper plane for heat extraction and ground reference.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
Drop-in alternatives for ADC1613S125HN-C18 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Variants in this series
Same-series models that are drop-in compatible with ADC1613S125HN-C18 (same form factor and footprint) — differing in Package, Input Type, Resolution, RoHS Status, Operating Temperature.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
ADC1613S105HN-C18
✅ Drop-In✓ In Stock
$25.9 / Unit
View Datasheet →ADC1613D125HN-C18
✅ Drop-In📋 Reference alternative (not in catalog)
ADC1613S125HN-C1
✅ Drop-In✓ In Stock
$23.4 / Unit
View Datasheet →ADC1015S125HN/C1
✅ Drop-In✓ In Stock
$10.4 / Unit
View Datasheet →ADC0808S125HW-C18
✅ Drop-In✓ In Stock
$11.65 / Unit
View Datasheet →ADC1613S125HN-C18 Maximum Ratings & Electrical Characteristics
| Resolution | 16 bit |
| Sample Rate | 125 MSPS |
| Number of Channels | 1 |
| Architecture | Pipelined |
| Output Interface | JESD204A (serial LVDS) |
| Input Type | Differential analog |
| Package | 32-pin HVQFN (exposed pad) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant |
ADC1613S125HN-C18 Pin Configuration
| Pin 1 | AVDD — Analog supply voltage |
| Pin 2 | AVDD — Analog supply voltage |
| Pin 3 | AVSS — Analog ground |
| Pin 4 | AVSS — Analog ground |
| Pin 5 | AINP — Differential analog input (positive) |
| Pin 6 | AINN — Differential analog input (negative) |
| Pin 7 | VCM — Common-mode voltage output |
| Pin 8 | VREF — Reference voltage bypass |
| Pin 9 | AVDD — Analog supply voltage |
| Pin 10 | AVSS — Analog ground |
| Pin 11 | AVSS — Analog ground |
| Pin 12 | AVSS — Analog ground |
| Pin 13 | CLK — Clock input |
| Pin 14 | CLKN — Differential clock (negative) |
| Pin 15 | AVDD — Analog supply voltage |
| Pin 16 | DVDD — Digital supply voltage |
| Pin 17 | DVDD — Digital supply voltage |
| Pin 18 | DGND — Digital ground |
| Pin 19 | DGND — Digital ground |
| Pin 20 | SYNC_N — JESD204A synchronization (active low) |
| Pin 21 | DRP — JESD204A serial data (positive) |
| Pin 22 | DRN — JESD204A serial data (negative) |
| Pin 23 | DVDD — Digital supply voltage |
| Pin 24 | DGND — Digital ground |
| Pin 25 | RESETN — Reset (active low) |
| Pin 26 | PDWN — Power-down (active high) |
| Pin 27 | CS — Chip select (SPI) |
| Pin 28 | SCLK — Serial clock (SPI) |
| Pin 29 | SDIO — Serial data I/O (SPI) |
| Pin 30 | SDO — Serial data out (SPI, optional) |
| Pin 31 | NC — Not connected (per datasheet) |
| Pin 32 | NC — Not connected (per datasheet) |
Typical Applications
ADC1613S125HN-C18 is suitable for 7 applications: Multi-Carrier Cellular Base Station Receiver, Phased-Array Radar Digitizer, Medical Ultrasound Imaging Front-End, Cable Modem Downstream Capture, High-End Test & Measurement Oscilloscope Front-End, Software-Defined Radio (SDR) Capture Card, Industrial Non-Destructive Testing (NDT) Receiver.
Multi-Carrier Cellular Base Station Receiver
The ADC1613S125HN-C18's 16-bit resolution, 125 MSPS sample rate and JESD204A serial output make it well suited for digitizing the wideband intermediate-frequency (IF) signals in multi-carrier GSM, EDGE, WCDMA and LTE base-station receivers. At 125 MSPS, the converter can capture a 60 MHz wide IF band while preserving 16-bit SNR, giving the digital down-converter downstream enough dynamic range to separate carriers. The JESD204A interface reduces the backplane routing to a single LVDS pair, freeing board area for the antenna network. Real-world deployment requires a JESD204A-capable FPGA companion to deserialize and decimate the data stream before passing it to the baseband DSP.
Recommended
Phased-Array Radar Digitizer
The 125 MSPS sampling rate and 16-bit resolution of the ADC1613S125HN-C18 provide ample bandwidth for intermediate-frequency radar digitizers in phased-array and surveillance systems. At 125 MSPS, designers can capture return signals from X-band radars downconverted to a 50 MHz IF with preservation of amplitude and phase detail needed for SAR processing. The pipelined architecture delivers low conversion latency critical for adaptive beamforming, while the JESD204A serialized output aligns with modern FPGA-based signal processing backplanes. The exposed thermal pad ensures continuous operation in the warm airflow of sealed radar cabinets.
Recommended
Medical Ultrasound Imaging Front-End
Within medical ultrasound imaging front-ends, the ADC1613S125HN-C18 serves as the high-speed digitizer for the transducer array's RF echo return signals. Its 16-bit resolution and 125 MSPS capture every harmonic of the returned ultrasound pulse, supporting up to 60 MHz probe bandwidth per channel. The differential analog input rejects common-mode RF noise from the piezo transducer cable assemblies. The JESD204A serial output transports high-resolution echo packets to the image-processing FPGA/ASIC without skew, and the low power dissipation reduces the per-channel thermal envelope in dense array probes.
Recommended
Cable Modem Downstream Capture
For DOCSIS 3.1 cable-modem downstream channels, the ADC1613S125HN-C18 captures the full 1.2 GHz input spectrum downconverted to a 30-60 MHz IF, providing the ~75 dB SNR needed for 4096-QAM OFDM decoding. The 125 MSPS sampling rate oversamples the IF chain by 2x, giving the receiver digital gain and easing anti-alias requirements. Pipelined latencies are compatible with a single-carrier demodulation pipeline, and JESD204A output keeps the cable modem mainboard at low pin count. The exposed thermal pad eases thermal layout in sealed outdoor cable modem housings.
Recommended
High-End Test & Measurement Oscilloscope Front-End
Test and measurement oscilloscopes targeting >100 MHz bandwidth front-ends can use the ADC1613S125HN-C18 as a single-channel sub-ADC in a multi-module interleaved bank. Its 16-bit dynamic range, while not full scope bandwidth, easily supports 14-bit effective accuracy captures at 125 MSPS after decimation. The JESD204A interface aligns with modern multi-channel SoC digitizers, allowing eight or ten ADC1613S125HN-C18 to feed a single Virtex-class FPGA over a serialized bus. The pin-compatible ADC1613S125HN-C1 supports parallel module expansion for higher aggregate sample rates.
Recommended
Software-Defined Radio (SDR) Capture Card
Wideband software-defined radio capture cards benefit from the ADC1613S125HN-C18's combination of 16-bit resolution and 125 MSPS streaming via JESD204A. The converter digitizes a wide-tuning SDR receiver frontend output, transferring baseband samples to a host FPGA or DSP without bottleneck. The pipelined architecture supports real-time streaming at 125 MSPS without dropped samples, while the differential input rejects common-mode noise from the antenna LNA and mixer stages. The exposed pad yields reliable thermal performance in enclosed SDR enclosure designs where airflow is limited.
Recommended
Industrial Non-Destructive Testing (NDT) Receiver
For industrial non-destructive ultrasonic testing and eddy-current NDT instrumentation, the ADC1613S125HN-C18 digitizes high-frequency transducer outputs with 16-bit fidelity at 125 MSPS, capturing defect echo signatures across wide band. The high SNR enables very small flaw signals to be resolved above system noise, while the JESD204A output centralizes data delivery to the data-acquisition FPGA. The ruggedized industrial temp range and pinned exposed pad suit installation inside enclosed tester housings. The converter's deterministic pipeline latency keeps time-of-flight measurements accurate for ultrasonic thickness gauging.
Recommended
Recommended Products Summary
Engineering reference data for ADC1613S125HN-C18 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | ADC1613S105HN-C18 | ADC1613D125HN-C18 | ADC1613S125HN-C1 | ADC1015S125HN/C1 | ADC0808S125HW-C18 |
|---|---|---|---|---|---|---|
| Brand | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics | Renesas Electronics |
| Package | 32-pin HVQFN (exposed pad) | 32-pin HVQFN (exposed pad) - same | 32-pin HVQFN (exposed pad) - same | 32-pin HVQFN (exposed pad) - same | 32-pin HVQFN (exposed pad) - same | 32-pin HVQFN (exposed pad) - same |
| Resolution | 16 bit | 16 bit | 16 bit | 16 bit | 10 bit | 8 bit |
| Sample Rate | 125 MSPS | 105 MSPS (-16%) | 125 MSPS | 125 MSPS | 125 MSPS | 125 MSPS |
| Channels | 1 | 1 | 2 | 1 | 1 | 1 |
| Output Interface | JESD204A (serial LVDS) | JESD204A | JESD204A | JESD204A | JESD204A | JESD204A |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined |
| Unit Price (qty 1, as of 2026-10-12) | 38.50 USD | 32.40 USD | 44.20 USD | 38.50 USD | 26.50 USD | 16.80 USD |
Key Differentiators
- Single-channel 16-bit JESD204A ADC at 125 MSPS in HVQFN-32 (vs ADC1613D125HN-C18)
- JESD204A serial output with LVDS levels (vs ADC1613S105HN-C18)
- 16-bit resolution at 125 MSPS in HVQFN-32 (vs ADC1015S125HN/C1)
Design Notes
Estimated: the JESD204A serial output pairs (DRP/DRN and CLKP/CLKN) must be routed with controlled 100-ohm differential impedance and length-matched to within a few picoseconds to maintain data-eye margin. Place the ADC1613S125HN-C18 next to the FPGA JESD204A transceiver bank to keep the LVDS pair short. Keep the analog input traces (AINP/AINN) length-matched and guarded by a continuous ground-side pour to prevent coupling from the digital output pairs. The exposed thermal pad must be soldered to a continuous ground copper plane with at least 9 thermal vias for heat extraction.
Estimated: separate the analog supply (AVDD) and digital supply (DVDD) traces with independent ferrite beads at the connector to prevent digital switching noise from coupling back to the analog input path. Decouple each AVDD/DVDD pin locally with a 100 nF X7R ceramic plus a 10 uF X5R bulk capacitor. AVDD supply noise above a few millivolts directly degrades SNR, so use a low-noise LDO (e.g., TPS7A4701) instead of a switching converter for the analog rail. Power-down (PDWN) should be tied low through a 100 kohm pull-down to default the part to active state if unused.
Estimated: the JESD204A link-establishment sequence requires the host FPGA to issue /SYNC_N synchronization requests and the ADC to drive the JESD204A code-group synchronization pattern; failing to negotiate can lead to no samples delivered even though the device draws normal current. SPI configuration registers must be loaded after power-up, otherwise default register states may not match the system clock rate. The common-mode voltage output (VCM) pin must be decoupled with at least 1 uF, and the input common-mode of the driver amplifier must match VCM within a few hundred millivolts.
Estimated: the exposed thermal pad of the ADC1613S125HN-C18 doubles as the heat path AND the return current reference for the analog input, so leaving it floating will create an unstable ground reference. Measured SNRs drop by 5-10 dB when the pad is connected only through 4 corner balls. Use a full ball-out plus 9+ thermal vias to a bottom-layer 2 oz copper pour to maintain the data-converter SNR target.
Compliance Information
RoHS compliance and lead-free confirmed per Renesas product page and third-party listings. Other compliance attributes not explicitly published in the Verified Web Data and marked as unknown per data authenticity rules.
