ADC32J44IRGZ25 - Dual 14-Bit 125MSPS ADC w/ JESD204B | TI
Référence : ADC32J44IRGZ25 ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $68.5 | $68,50 |
| 10 | $61.2 | $612,00 |
| 100 | $54.75 | $5 475,00 |
| 500 | $47.8 | $23 900,00 |
| 1 000 | $42.1 | $42 100,00 |
ADC32J44IRGZ25 Présentation
An analog-to-digital converter (ADC) is a data-converter integrated circuit that samples continuous-time analog input signals and produces discrete-time binary codes at its output. ADCs sit inside the broader signal-chain hierarchy: sensor/IF -> analog front end (filter, amp) -> ADC -> digital processor (FPGA, ASIC, DSP). High-speed pipeline ADCs such as the ADC32J44 are widely used in communications, test and measurement, and defense electronics where both sampling rate and dynamic range are critical.
The ADC32J44IRGZ25 combines high linearity with ultra-low power: SNR of 72.2 dBFS and SFDR of 87 dBc at 70 MHz input, with channel-to-channel isolation of 105 dB. It integrates a flexible input clock buffer (divide-by-1, -2, -4), an internal dither engine, and a single 1.8 V supply. The JESD204B interface supports up to 3.125 Gbps lane rates, deterministic latency, and synchronization across multiple devices via SYSREF.
Architecturally, the part uses a multi-stage pipelined core with digital error correction and on-chip dither to improve small-signal linearity. Each channel has its own track-and-hold and reference buffer; the digital backend packs the two channel streams into 8B/10B-encoded lanes and serializes them out through the JESD204B link, offloading the FPGA from wide LVDS buses.
Typical applications include multi-carrier GSM/LTE base-station receivers, software-defined radio (SDR) platforms, radar and electronic-warfare signal capture, and high-speed digitizers for oscilloscopes and spectrum analyzers. In any of these uses the ADC32J44IRGZ25 is paired with a TI clock jitter cleaner and an FPGA/ASIC JESD204B receiver.
When designing in this part, plan the PCB layout carefully: keep the analog input traces length-matched and 50-ohm controlled-impedance, place the AVDD/AVSS decoupling capacitors within 2 mm of the supply pins, and isolate the analog and digital ground returns to avoid coupling switching noise into the input stage. A TI LM95233 or equivalent thermal sensor is recommended for monitoring junction temperature in dense systems.
This page combines distributor pricing, drop-in alternatives, and practical design notes that go beyond the manufacturer datasheet to help engineers select, source, and lay out the ADC32J44IRGZ25 with confidence.
Alternatives de remplacement direct pour ADC32J44IRGZ25 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec ADC32J44IRGZ25 (même facteur de forme et même empreinte) — différant par Package, Number of Channels, Resolution, Operating Temperature Range, Digital Interface.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
ADC32J45IRGZ25
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
ADC32J43IRGZ25
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
ADC32J42IRGZ25
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
ADC32J24IRGZ25
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
ADC32J25IRGZ25
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
ADS62P48IRGC25
✅ Remplacement direct✓ En stock
$49.2 / unité
Voir la fiche technique →ADS6242IRGZR
✅ Remplacement direct✓ En stock
$18.25 / unité
Voir la fiche technique →ADC32J44IRGZ25 Valeurs maximales et caractéristiques électriques
| Manufacturer | Texas Instruments |
| Series | ADC32J4x |
| Number of Channels | 2 |
| Résolution | 14 bit |
| Sampling Rate (max) | 125 MSPS |
| Architecture | Pipelined |
| Input Type | Differential |
| Data Interface | JESD204B |
| Number of Lanes | Up to 2 |
| Max Lane Rate | 3.125 Gbps |
| Supply Voltage (Analog) | 1.8 V |
| Supply Voltage (Digital) | 1.8 V |
| Power Consumption | 227 mW/Ch at 160 MSPS |
| SNR | 72.2 dBFS at fIN = 70 MHz |
| SFDR | 87 dBc at fIN = 70 MHz |
| Channel Isolation | 105 dB |
| Température de fonctionnement | -40C to +85C (Industrial) |
| Boîtier | 48-VQFN (7x7 mm) |
| Type de montage | Surface Mount |
| Statut RoHS | Compliant |
Configuration des broches de ADC32J44IRGZ25
| Broche 1 | VA11 — Analog 1.8 V supply |
| Broche 2 | INAP — Channel A positive analog input |
| Broche 3 | INAM — Channel A negative analog input |
| Broche 4 | VCM_A — Channel A common-mode voltage bypass |
| Broche 5 | VA11 — Analog 1.8 V supply |
| Broche 6 | VREF — Voltage reference bypass |
| Broche 7 | VA19 — Analog 1.9 V internal LDO output |
| Broche 8 | INBP — Channel B positive analog input |
| Broche 9 | INBM — Channel B negative analog input |
| Broche 10 | VCM_B — Channel B common-mode voltage bypass |
| Broche 11 | VA11 — Analog 1.8 V supply |
| Broche 12 | GND — Analog ground |
| Broche 13 | CLK+ — Differential clock input positive |
| Broche 14 | CLK- — Differential clock input negative |
| Broche 15 | GND — Clock ground |
| Broche 16 | SYSREF+ — JESD204B SYSREF positive |
| Broche 17 | SYSREF- — JESD204B SYSREF negative |
| Broche 18 | SYNC~ — JESD204B sync request |
| Broche 19 | RESET — Hardware reset, active low |
| Broche 20 | PDN — Power-down, active high |
| Broche 21 | SCLK — SPI clock |
| Broche 22 | SDI — SPI serial data in |
| Broche 23 | SDO — SPI serial data out |
| Broche 24 | SEN — SPI chip enable, active low |
| Broche 25 | GND — Digital ground |
| Broche 26 | VD11 — Digital 1.8 V supply |
| Broche 27 | GND — Digital ground |
| Broche 28 | TX0+ — JESD204B lane 0 output positive |
| Broche 29 | TX0- — JESD204B lane 0 output negative |
| Broche 30 | TX1+ — JESD204B lane 1 output positive |
| Broche 31 | TX1- — JESD204B lane 1 output negative |
| Broche 32 | GND — Digital ground |
| Broche 33 | VD11 — Digital 1.8 V supply |
| Broche 34 | GND — Digital ground |
| Broche 35 | NC — Not connected (per datasheet) |
| Broche 36 | NC — Not connected (per datasheet) |
| Broche 37 | TEST1 — Factory test pin, leave floating |
| Broche 38 | TEST2 — Factory test pin, leave floating |
| Broche 39 | TEST3 — Factory test pin, leave floating |
| Broche 40 | VA11 — Analog 1.8 V supply |
| Broche 41 | GND — Analog ground |
| Broche 42 | VA11 — Analog 1.8 V supply |
| Broche 43 | GND — Analog ground |
| Broche 44 | VA11 — Analog 1.8 V supply |
| Broche 45 | GND — Analog ground |
| Broche 46 | VA11 — Analog 1.8 V supply |
| Broche 47 | GND — Analog ground |
| Broche 48 | GND — Analog ground |
Applications typiques
ADC32J44IRGZ25 convient pour 6 applications: Multi-Carrier GSM/LTE Base Station Receiver, Software Defined Radio (SDR) Platform, Phased-Array Radar Signal Capture, High-Speed Digital Oscilloscope and Spectrum Analyzer, Medical Ultrasound Imaging Receiver, Industrial Vibration and Condition Monitoring.
Multi-Carrier GSM/LTE Base Station Receiver
The ADC32J44IRGZ25 digitizes multi-carrier cellular signals at the base-station receiver IF, where its 72.2 dBFS SNR and 87 dBc SFDR at 70 MHz preserve the modulation error ratio required for 4G LTE and 5G NR carriers. The dual-channel architecture simultaneously samples the I and Q baseband paths, while the JESD204B interface streams data to the FPGA/CPU baseband processor at up to 3.125 Gbps per lane. Compared with LVDS-interface ADCs, the JESD204B output eliminates 28+ data lines per channel, simplifying PCB routing in dense radio units.
Recommandé
Software Defined Radio (SDR) Platform
In SDR platforms the ADC32J44IRGZ25 provides the dual matched-channel sampling needed for direct-conversion I/Q digitization, with 105 dB channel isolation suppressing LO leakage in quadrature demodulators. The 125 MSPS sample rate covers up to 62.5 MHz of complex bandwidth, suitable for narrowband tactical radio and commercial SDR applications. The 1.8 V single supply and ~200 mW per channel power budget keep the thermal design within typical sealed SDR enclosure limits.
Recommandé
Phased-Array Radar Signal Capture
Phased-array radar and electronic-warfare receivers use the ADC32J44IRGZ25 to digitize multiple antenna-element signals in parallel, with the JESD204B interface enabling deterministic latency for beamforming alignment via SYSREF. The 125 MSPS sample rate supports intermediate-frequency bandwidths typical of S-band and C-band radar pulse processing. Channel-to-channel matching within the integrated device is critical for beam-pattern accuracy, and TI specifies this as part of the AC test parameters.
Recommandé
High-Speed Digital Oscilloscope and Spectrum Analyzer
Test and measurement instruments such as bench oscilloscopes and spectrum analyzers use the ADC32J44IRGZ25 as a two-channel front-end digitizer for time-domain and frequency-domain signal capture. The 14-bit resolution and 72 dBFS SNR deliver 11+ effective bits at low input frequencies, supporting accurate amplitude and modulation measurements. The JESD204B interface is well suited to multi-channel oscilloscope architectures where 4 to 8 ADCs must be synchronized to a common trigger.
Recommandé
Medical Ultrasound Imaging Receiver
Medical ultrasound beamformers use the ADC32J44IRGZ25 to digitize analog receive signals from piezo transducer arrays, where its 14-bit resolution and 125 MSPS sample rate support 16 to 32 channel beamforming at typical 5 to 40 MHz IF frequencies. The low 200 mW-per-channel power budget is critical for patient-handling cart applications where heat dissipation is constrained, and the JESD204B interface consolidates 32 ADC channels onto a small number of high-speed serial lanes to a central FPGA.
Recommandé
Industrial Vibration and Condition Monitoring
Industrial condition-monitoring systems (vibration analysis on motors, pumps, gearboxes) use the ADC32J44IRGZ25 to digitize dual-axis accelerometer signals, capturing frequency content up to 50 kHz with 14-bit dynamic range. The -40C to +85C industrial temperature grade supports deployment in factory-floor enclosures and outdoor equipment. The JESD204B interface enables multiple sensor nodes to stream data back to a central processor over fiber or shielded twisted pair, simplifying cable harness design.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour ADC32J44IRGZ25 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | ADC32J45IRGZ25 | ADC32J43IRGZ25 | ADC32J24IRGZ25 | ADS62P48IRGC25 |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 48-VQFN (7x7 mm) | 48-VQFN (7x7 mm) - same | 48-VQFN (7x7 mm) - same | 48-VQFN (7x7 mm) - same | 48-VQFN (7x7 mm) - same |
| Resolution | 14 bit | 14 bit | 14 bit | 12 bit | 12 bit |
| Max Sample Rate | 125 MSPS | 160 MSPS | 80 MSPS | 125 MSPS | 210 MSPS |
| Number of Channels | 2 | 2 | 2 | 2 | 2 |
| Data Interface | JESD204B | JESD204B | JESD204B | JESD204B | LVDS |
| SNR at 70 MHz | 72.2 dBFS | 72.2 dBFS | 72.2 dBFS | 70 dBFS | 70.4 dBFS |
| Power per Channel | ~200 mW at 125 MSPS | 227 mW at 160 MSPS | ~140 mW at 80 MSPS | 180 mW at 125 MSPS | 430 mW at 210 MSPS |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
Principaux différenciateurs
- Pin-compatible 160 MSPS upgrade path within same family (vs ADC32J45IRGZ25)
- JESD204B interface vs legacy LVDS for high-channel-count systems (vs ADS62P48IRGC25)
- Lower power at equivalent sample rate than competing 12-bit ADCs (vs ADS62P48IRGC25)
Notes de conception
Route the differential analog input pairs (INAP/INAM and INBP/INBM) as 100-ohm differential stripline or microstrip with length matching within 0.5 mm to preserve SNR and channel-to-channel phase alignment. Keep the analog input traces on the top layer over a continuous analog ground pour; vias should be stitched every 2 mm to suppress return-path inductance. Reference the TI ADC32J44EVM user guide for the recommended evaluation board stack-up.
Decouple each VA11 pin with a 0.1 uF X7R ceramic placed within 2 mm of the pad, plus a 10 uF bulk capacitor per rail. Use a ferrite bead or pi filter between the analog and digital 1.8 V supplies to prevent switching noise from the JESD204B serializer from coupling into the input sample-and-hold. The exposed thermal pad (pin 0) must be soldered to a 5x5 mm minimum ground pour for thermal dissipation and AC ground return.
Clock jitter directly degrades SNR according to the formula SNR_JITTER = 20*log10(1/(2*pi*fIN*tJ)). For 70 MHz input and 72 dBFS SNR target, the total clock jitter budget (including CLK buffer, distribution, and ADC aperture) is approximately 250 fs RMS. Use an LMK04828 or LMK04832 jitter cleaner to source CLK and SYSREF; SYSREF must be a submultiple of the local multiframe clock and DC-balanced for deterministic JESD204B link setup.
Do not float the exposed thermal pad; doing so causes a 5-10 C junction temperature rise and degrades linearity. The TEST1/TEST2/TEST3 pins must be left floating - do not pull them to ground or supply, as the datasheet uses them for factory trim. Ensure RESET is held low for at least 1 us after the 1.8 V supplies are stable, then released, before initiating JESD204B link bring-up via SPI writes to register 0x00.
Informations de conformité
RoHS compliant per DigiKey product listing. Industrial temperature grade -40C to +85C but not AEC-Q100 qualified; for automotive applications contact TI for Q1-qualified variants. Conflict-minerals compliance status from TI product page.
