DSPIC33CK128MC105T-I/M7 - 16-bit DSC 128KB Flash 48-VQFN | Microchip
Référence : DSPIC33CK128MC105T-I/M7 ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $5.85 | $5,85 |
| 10 | $5.27 | $52,70 |
| 100 | $4.68 | $468,00 |
| 500 | $4.1 | $2 050,00 |
| 1 000 | $3.65 | $3 650,00 |
DSPIC33CK128MC105T-I/M7 Présentation
A digital signal controller combines the deterministic arithmetic capability of a digital signal processor (DSP) with the peripheral integration and low-power modes of a microcontroller (MCU). Within the power-management hierarchy of embedded systems, the dsPIC33CK family sits at the intersection of general-purpose MCUs and dedicated motor-control DSPs, offering single-cycle MAC/DSP instructions alongside hardened control peripherals.
Key features include the single 16-bit dsPIC DSC core operating up to 100 MIPS, on-chip operational amplifiers for current-sense signal conditioning, a 12-bit high-speed ADC for simultaneous multi-channel sampling, and high-resolution PWM outputs supporting Field-Oriented Control (FOC). The M7 package suffix denotes the industrial-grade 48-VQFN 6x6 mm option, and the T suffix indicates tape-and-reel delivery for automated assembly.
Architecturally, the device pairs the enhanced flash (with ECC and live update support) to multiple dedicated DMA channels and interrupt vectors, keeping deterministic loop closure times short. The DSP engine supports single-cycle MAC and hardware division, while the flexible clock system (internal fast RC oscillator with PLL or external crystal) allows designers to trade clock frequency against power consumption. Peripherals include UART, SPI, I2C, CLC configurable logic, and multiple 16-bit timers.
Typical applications include brushless DC and PMSM motor control (sensorless FOC), digital power supplies (LLC, totem-pole PFC), battery chargers, and industrial sensing front-ends where the on-chip op-amps amplify shunt currents before the 12-bit ADC samples them.
Design consideration: decouple AVDD and VDD separately and provide the dedicated VCAP bulk capacitor per the power diagram; the internal LDO requires it for stable core regulation at 100 MIPS operation.
This page synthesizes distributor pricing, drop-in family alternatives, design notes, and application guidance not found in the manufacturer datasheet. Pricing shown is as of 2026-09-22.
Alternatives de remplacement direct pour DSPIC33CK128MC105T-I/M7 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec DSPIC33CK128MC105T-I/M7 (même facteur de forme et même empreinte) — différant par Core, ADC Resolution, Data Bus Width, Operating Temperature, Package.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
DSPIC33CK128MC105-I/M7
✅ Remplacement direct✓ En stock
$1.98 / unité
Voir la fiche technique →DSPIC33CK256MC105T-I/M7
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
DSPIC33CK64MC105T-I/M7
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
DSPIC33CK128MC105T-E/M7
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
DSPIC33CK128MC505T-I/M7
✅ Remplacement direct ⚠️ Spécifications non vérifiées✓ En stock
$3.98 / unité
Voir la fiche technique →DSPIC33CK128MC105T-I/M7 Valeurs maximales et caractéristiques électriques
| Core | dsPIC33CK 16-bit DSC |
| Core Clock | up to 100 MHz (100 MIPS) |
| Flash Program Memory | 128 KB (128K x 16) |
| SRAM | 16 KB |
| Tension d'alimentation | 3.0 V to 3.6 V |
| Température de fonctionnement | -40C to +85C (I grade) |
| Boîtier | 48-VQFN (6x6 mm), exposed pad |
| Type de montage | Surface Mount |
| ADC Resolution | 12-bit |
| On-chip Op-Amps | Yes (integrated op-amps) |
| PWM | High-resolution PWM for motor control |
| DMA | Yes (multiple DMA channels) |
| Communication Interfaces | UART, SPI, I2C |
| Packaging Suffix | T = Tape & Reel |
| Largeur du bus de données | 16-bit |
| Program Memory Type | Flash |
Configuration des broches de DSPIC33CK128MC105T-I/M7
| Broche 1 | MCLR — Master clear reset input / programming voltage |
| Broche 2 | AN0/RA0 — Analog input 0 / digital I/O |
| Broche 3 | AN1/RA1 — Analog input 1 / digital I/O |
| Broche 4 | VSS — Ground reference |
| Broche 5 | AN2/RA2 — Analog input 2 / digital I/O |
| Broche 6 | AN3/RA3 — Analog input 3 / digital I/O |
| Broche 7 | VDD — Power supply 3.0-3.6 V |
| Broche 8 | PGD/EMUD1/RB1 — Programming data / debug / digital I/O |
| Broche 9 | PGC/EMUC1/RB0 — Programming clock / debug / digital I/O |
| Broche 10 | AN4/RB4 — Analog input 4 / digital I/O |
| Broche 11 | AN5/RB5 — Analog input 5 / digital I/O |
| Broche 12 | AN6/RB6 — Analog input 6 / digital I/O |
| Broche 13 | AN7/RB7 — Analog input 7 / digital I/O |
| Broche 14 | AN8/RB8 — Analog input 8 / digital I/O |
| Broche 15 | AN9/RB9 — Analog input 9 / digital I/O |
| Broche 16 | VSS — Ground reference |
| Broche 17 | VDD — Power supply |
| Broche 18 | AN10/RB10 — Analog input 10 / digital I/O |
| Broche 19 | AN11/RB11 — Analog input 11 / digital I/O |
| Broche 20 | PWM1H/RC0 — High-resolution PWM output 1H / digital I/O |
| Broche 21 | PWM1L/RC1 — High-resolution PWM output 1L / digital I/O |
| Broche 22 | PWM2H/RC2 — High-resolution PWM output 2H / digital I/O |
| Broche 23 | PWM2L/RC3 — High-resolution PWM output 2L / digital I/O |
| Broche 24 | PWM3H/RC4 — High-resolution PWM output 3H / digital I/O |
| Broche 25 | PWM3L/RC5 — High-resolution PWM output 3L / digital I/O |
| Broche 26 | VSS — Ground reference |
| Broche 27 | OA1OUT/RC6 — Op-amp 1 output / digital I/O |
| Broche 28 | OA1IN+/AN12/RC7 — Op-amp 1 non-inverting input / analog / digital I/O |
| Broche 29 | OA1IN-/AN13/RC8 — Op-amp 1 inverting input / analog / digital I/O |
| Broche 30 | OA2OUT/RC9 — Op-amp 2 output / digital I/O |
| Broche 31 | OA2IN+/AN14/RD0 — Op-amp 2 non-inverting input / analog / digital I/O |
| Broche 32 | OA2IN-/AN15/RD1 — Op-amp 2 inverting input / analog / digital I/O |
| Broche 33 | OA3OUT/RD2 — Op-amp 3 output / digital I/O |
| Broche 34 | OA3IN+/RD3 — Op-amp 3 non-inverting input / digital I/O |
| Broche 35 | OA3IN-/RD4 — Op-amp 3 inverting input / digital I/O |
| Broche 36 | PWM4H/RD5 — High-resolution PWM output 4H / digital I/O |
| Broche 37 | PWM4L/RD6 — High-resolution PWM output 4L / digital I/O |
| Broche 38 | SOSCI/RD7 — Secondary oscillator input / digital I/O |
| Broche 39 | SOSCO/RD8 — Secondary oscillator output / digital I/O |
| Broche 40 | VDD — Power supply |
| Broche 41 | VCAP — Internal core LDO bulk capacitor |
| Broche 42 | AVSS — Analog ground |
| Broche 43 | AVDD — Analog power supply |
| Broche 44 | OSC1/RD9 — Primary oscillator input / digital I/O |
| Broche 45 | OSC2/RC13 — Primary oscillator output / digital I/O |
| Broche 46 | VSS — Ground reference |
| Broche 47 | SCL/RD10 — I2C clock / digital I/O |
| Broche 48 | SDA/RD11 — I2C data / digital I/O |
Applications typiques
DSPIC33CK128MC105T-I/M7 convient pour 6 applications: BLDC/PMSM Sensorless Motor Control, Digital Power Conversion, Industrial Sensing Front-Ends, Battery Management and Chargers, Industrial Automation and Robotics, Embedded Systems / General Purpose Control.
BLDC/PMSM Sensorless Motor Control
The DSPIC33CK128MC105T-I/M7 is purpose-built for sensorless Field-Oriented Control of brushless DC and permanent-magnet synchronous motors. Its 100 MIPS core executes single-cycle MAC instructions so the FOC current loop closes within one PWM period even at high electrical speeds. The integrated op-amps amplify phase-current shunt voltages in-line, and the 12-bit ADC samples all three phases with the high-resolution PWM triggering synchronized conversions, eliminating external analog front-end components. Designers should budget ISR execution time to stay under the PWM period at maximum motor speed; the deterministic interrupt latency of the dsPIC33CK core makes this calculation reliable.
Recommandé
Digital Power Conversion
Digital power supplies such as LLC converters, totem-pole PFC stages, and synchronous buck regulators benefit from this DSC's high-resolution PWM and fast control loop. The 100 MIPS core supports single- or double-update control at switching frequencies used in modern AC-DC and DC-DC designs, while PWM dead-time and phase-shift control are handled in hardware with fine resolution to minimize body-diode conduction losses. The 12-bit ADC provides output-voltage and current telemetry with DMA offloading of sample buffers. Compensator coefficients can be updated on the fly, enabling adaptive mode transitions between burst, CC, and CV operation in battery chargers and adapters.
Recommandé
Industrial Sensing Front-Ends
The on-chip op-amps combined with the 12-bit ADC make this device a compact analog signal-chain solution for industrial sensing: pressure transducers, thermocouple conditioning via the internal references, and current monitoring all fit without external amplifier ICs. Gain and offset of the integrated op-amps are register-configurable, allowing run-time reconfiguration across sensor variants on one PCB. UART, SPI, and I2C interfaces push processed data to PLC networks or gateways, and the DMA engine sustains streaming without CPU intervention. The -40C to +85C industrial temperature grade covers factory-floor environments without component derating.
Recommandé
Battery Management and Chargers
Battery charging systems use this DSC for CC/CV profile control, coulomb counting, and safety supervision. The high-resolution PWM drives the power stage with low ripple, the 12-bit ADC reads cell voltages and current through the integrated op-amps, and the 128 KB flash stores charging profiles, logging, and communication stacks simultaneously. Multiple low-power modes support always-on battery supervision with minimal draw, waking on comparator or timer events. The deterministic core also implements safety-critical monitoring routines such as over-current and over-temperature cutoffs with tightly bounded response times, supporting layered protection architectures in smart chargers and power banks.
Recommandé
Industrial Automation and Robotics
In automation nodes, servo drives, and robotic joints, this controller merges motor control and system supervision on one chip. The 100 MIPS DSP engine closes servo current loops while the general-purpose peripherals handle encoders, limit switches via CLC configurable logic, and Modbus/UART communication to PLCs. The 16 KB RAM accommodates fieldbus buffers and trajectory calculations, and the 128 KB flash supports protocol stacks plus firmware update mechanisms. Multiple timers coordinate motion sequencing. Using one DSC for both control and communication reduces BOM count versus separate MCU-plus-driver architectures common in compact actuator designs.
Recommandé
Embedded Systems / General Purpose Control
For general embedded control where some DSP throughput is occasionally needed - filtering, FFT-based diagnostics, or audio-tone generation - this DSC offers MCU-style development with DSP headroom. The MPLAB X and XC16 toolchain with MCC code generation lowers barrier to entry, while the peripheral ecosystem (UART, SPI, I2C, CLC, timers) covers typical I/O needs. The 48-VQFN 6x6 mm footprint balances GPIO count against board area for cost-sensitive products. The tape-and-reel T ordering code suits high-volume contract manufacturing with automated placement, and the industrial temperature grade avoids qualifying separate consumer SKUs.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour DSPIC33CK128MC105T-I/M7 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | DSPIC33CK128MC105-I/M7 | DSPIC33CK256MC105T-I/M7 | DSPIC33CK64MC105T-I/M7 | DSPIC33CK128MC105T-E/M7 |
|---|---|---|---|---|---|
| Package | 48-VQFN (6x6) | 48-VQFN (6x6) - same | 48-VQFN (6x6) - same | 48-VQFN (6x6) - same | 48-VQFN (6x6) - same |
| Brand | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology | Microchip Technology |
| Core / Performance | 16-bit dsPIC33CK, up to 100 MIPS | 16-bit, up to 100 MIPS | 16-bit, up to 100 MIPS | 16-bit, up to 100 MIPS | 16-bit, up to 100 MIPS |
| Flash Memory | 128 KB | 128 KB | 256 KB | 64 KB | 128 KB |
| SRAM | 16 KB | 16 KB | 16 KB | 16 KB | 16 KB |
| Packaging Delivery | Tape & Reel (T) | Tray/Tube | Tape & Reel | Tape & Reel | Tape & Reel |
| Integrated Op-Amps / 12-bit ADC / PWM | Yes / Yes / Yes | Yes / Yes / Yes | Yes / Yes / Yes | Yes / Yes / Yes | Yes / Yes / Yes |
Principaux différenciateurs
- Balanced 128 KB flash with full peripheral set (vs DSPIC33CK64MC105T-I/M7)
- Cost-optimized vs the 256 KB sibling (vs DSPIC33CK256MC105T-I/M7)
- Tape-and-reel delivery for automated assembly (vs DSPIC33CK128MC105-I/M7)
Notes de conception
The device regulates its core from the 3.3 V rail through an internal LDO whose output appears on the VCAP pin. Provide the bulk capacitor on VCAP exactly as specified in the power-delivery section of the manufacturer datasheet - wrong capacitance or excessive ESR destabilizes the core and causes erratic execution at 100 MIPS. Decouple each VDD pin with 100 nF ceramic capacitors placed within 2 mm, and isolate AVDD from the digital rail with a ferrite bead plus a dedicated 1 uF capacitor for best ADC performance.
The 48-VQFN 6x6 mm package has an exposed thermal pad that must be soldered to a grounded copper pour - it carries the majority of VSS current, not just heat. Use a 4x4 via array under the pad connected to the ground plane for lowest inductance. Keep the PWM output traces to gate drivers short and separated from the op-amp input traces carrying microvolt-level shunt signals; a ground guard ring around OA input traces reduces crosstalk from PWM edges.
Do not reconfigure the integrated op-amps and their ADC input assignments independently without checking the multiplexed pin maps - on dsPIC33CK devices the op-amp input pins share analog multiplexer channels, and an incorrect RPx pin selection silently disconnects the current-sense signal, producing zero-current readings that mimic a broken shunt. Validate analog channel mapping in MCC before PCB layout freeze. Also note the I-grade device is not rated for extended-temperature automotive use; select the E-grade sibling (DSPIC33CK128MC105T-E/M7) for hotter environments.
Informations de conformité
Compliance data for this exact ordering code was not present in the retrieved web data. Confirm RoHS/REACH status via Microchip's Environmental Data lookup. This is a standard industrial (I-grade) part, not an AEC-Q100 automotive variant.
