EP1810JC35 - 48 Macrocell Classic EPLD 35ns CMOS PLCC-68 | Altera
Référence : EP1810JC35 ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $18.5 | $18,50 |
| 10 | $16.2 | $162,00 |
| 100 | $13.85 | $1 385,00 |
| 500 | $11.4 | $5 700,00 |
| 1 000 | $9.75 | $9 750,00 |
EP1810JC35 Présentation
A Complex Programmable Logic Device (CPLD / EPLD) is a non-volatile, instant-on programmable logic device that sits hierarchically between discrete 74-series glue logic and larger FPGA fabrics. It combines an AND/OR programmable array with registered or combinational macrocell outputs, retaining its configuration without external boot memory. Classic EPLDs such as the EP1810JC35 are widely used for deterministic, single-clock-cycle logic replacement where FPGAs would be over-sized or over-priced and where PAL/GAL devices lack the macrocell count. As a logic integration category, EPLDs belong to programmable logic devices, then programmable logic, then digital semiconductors.
Key features of the EP1810JC35 include a 35 ns tPD (pin-to-pin delay), 5.25 V maximum VCC, commercial 0 C to +70 C operating range, ceramic J-lead PLCC-68 package with windowed UV-erasable die, and JTAG-/programmer-based configuration via Altera's MAX+plus II or A+plus development flow. The 48 macrocells are organized into four Logic Array Blocks (LABs) sharing a programmable interconnect array (PIA), giving the part deterministic, predictable timing. Compared to GAL/PAL devices, the EP1810 delivers higher macrocell density, multiple dedicated clock inputs, and architectural support for both D/T/JK flip-flop macrocell modes.
Architecturally, the EP1810JC35 uses a CMOS EPROM-cell-based AND array driving a fixed OR array, with each macrocell offering configurable register polarity, output enable, and feedback. The 35 ns speed grade is one of three commonly offered grades (-25, -35, -45 ns) within the same PLCC-68 pinout, allowing designers to trade timing margin against cost without changing board layout. The J-lead ceramic package supports both windowed (erasable) and OTP usage; the 'C' suffix denotes commercial temperature grade.
Typical applications include peripheral and memory-interface glue logic in legacy computing platforms, address decoding and wait-state generation in 80C186/80386-based embedded designs, bus arbitrators and interrupt controllers, high-speed state machines, and channelized industrial control logic. The 5 V tolerance and CMOS input structure make it well-suited to TTL-compatible buses that have since migrated to 3.3 V microcontrollers via simple level shifters. Programmable logic devices such as the EP1810JC35 are still supported for long-lifecycle defense and aerospace programs that value the part's ceramic packaging and proven reliability.
When designing with the EP1810JC35, observe the 5.25 V absolute maximum VCC (use a regulated 5 V rail), provide proper decoupling (one 0.1 uF per VCC pin plus a bulk 10 uF), and route the dedicated clock and clear pins with controlled-impedance traces. Because the device is OTP/UV-erasable depending on lid variant, design engineers should plan for one-time programming orceramic-windowed erasure cycles during prototyping.
This page synthesizes distributor pricing, drop-in alternatives, application examples and practical design notes not collated in the manufacturer datasheet, helping engineers source or substitute the EP1810JC35 for new designs or legacy repairs.
Alternatives de remplacement direct pour EP1810JC35 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EP1810JC35 (même facteur de forme et même empreinte) — différant par Technology, Package, Macrocells, Family, Mounting Type.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EP1810JC-25
✅ Remplacement direct✓ En stock
$6.8 / unité
Voir la fiche technique →EP1810JC-45
✅ Remplacement direct✓ En stock
$21.1 / unité
Voir la fiche technique →EP1810GC-35
✅ Remplacement direct✓ En stock
$177.12 / unité
Voir la fiche technique →EP1810GC-35AB
✅ Remplacement direct✓ En stock
$9.95 / unité
Voir la fiche technique →EP1810GI-45
✅ Remplacement direct✓ En stock
$56.4 / unité
Voir la fiche technique →EP1810JC35 Valeurs maximales et caractéristiques électriques
| Family | Altera Classic EPLD |
| Product Type | UV-erasable / OTP Complex PLD (EPLD) |
| Macrocells | 48 |
| Propagation Delay (tPD) | 35 ns |
| Fréquence d'horloge maximale | 40 MHz |
| Supply Voltage (VCC max) | 5.25 V |
| Process Technology | CMOS EPROM cell |
| Température de fonctionnement | 0 C to +70 C (Commercial) |
| Boîtier | PLCC-68 (J-lead, ceramic) |
| Package Code | QCCJ |
| Terminal Form | J-BEND |
| Number of Terminals | 68 |
| Programming | UV-erase (windowed) or OTP |
| Development Tool | Altera MAX+plus II / A+plus |
Configuration des broches de EP1810JC35
| Broche 1 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 2 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 3 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 4 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 5 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 6 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 7 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 8 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 9 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 10 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 11 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 12 | GND — Ground |
| Broche 13 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 14 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 15 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 16 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 17 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 18 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 19 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 20 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 21 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 22 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 23 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 24 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 25 | GND — Ground |
| Broche 26 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 27 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 28 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 29 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 30 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 31 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 32 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 33 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 34 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 35 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 36 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 37 | GND — Ground |
| Broche 38 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 39 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 40 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 41 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 42 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 43 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 44 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 45 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 46 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 47 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 48 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 49 | GND — Ground |
| Broche 50 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 51 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 52 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 53 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 54 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 55 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 56 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 57 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 58 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 59 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 60 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 61 | GND — Ground |
| Broche 62 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 63 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 64 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 65 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 66 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 67 | I/O — User I/O pin (macrocell bidirectional) |
| Broche 68 | VCC — +5 V supply |
Applications typiques
EP1810JC35 convient pour 6 applications: Legacy 80C186/80386 Address Decoding, Bus Arbitrator and DMA Glue Logic, High-Speed State Machine Controllers, Memory Interface Wait-State Generator, Industrial PLC I/O Expansion, Legacy Printer and Plotter Controller Logic.
Legacy 80C186/80386 Address Decoding
The EP1810JC35 fits legacy 80C186 and 80386 embedded designs because its 48 macrocells and 35 ns tPD easily absorb the 20-25 ns address-to-select decode budget of those 8-16 MHz microprocessors. Its 5 V TTL-compatible I/O mates directly with the processor's bus without level shifters, and its 48 macrocells can implement 12-16 chip-select lines plus wait-state logic in a single device. The non-volatile UV-erasable configuration also means no boot ROM is required, simplifying board bring-up. Source: Altera Classic EPLD datasheet and 80C186 peripheral-interface reference designs.
Recommandé
Bus Arbitrator and DMA Glue Logic
In ISA/PCI-to-local-bus bridge designs, the EP1810JC35 arbitrates bus requests, generates grant strobes and consolidates DMA acknowledge signals using its registered macrocells and dedicated clock inputs. The 35 ns tPD meets the 8 MHz ISA bus arbitration window with comfortable margin, while the 48 macrocells handle up to 8 simultaneous bus masters with priority encoding. The deterministic timing of EPLD architecture avoids the metastability risks that plague CPLD-based designs at the same node.
Recommandé
High-Speed State Machine Controllers
The EP1810JC35 implements multi-state sequential controllers for industrial automation, replacing 4-6 discrete 22V10 GALs with a single 48-macrocell device. Its 35 ns tPD supports 40 MHz state-machine clock rates, while the four LABs allow natural partition of FSM logic, output decode, and registered flag logic. The J-lead ceramic package and 0-70 C commercial range suit factory-floor enclosures. Source: Classic EPLD datasheet typical application section and Altera application note 33.
Recommandé
Memory Interface Wait-State Generator
Between a 25 MHz 68k CPU and slow SRAM/EPROM, the EP1810JC35 generates variable wait-state insertion based on address decode and memory-type inputs. Its 48 macrocells encode the wait-state counter, ready-stretch logic and DTACK generator in one device, eliminating two TTL chips. The 5 V tolerance matches the 68k bus directly, and the ceramic PLCC-68 footprint survives through-hole rework in long-lifecycle defense programs.
Recommandé
Industrial PLC I/O Expansion
In programmable-logic-controller I/O modules, the EP1810JC35 multiplexes 32-48 discrete inputs to a 16-bit backplane bus, providing input debouncing, edge detection and pulse-stretching in one device. The 35 ns tPD supports 40 MHz backplane operation, and the 48 macrocells encode debounce filters (typ. 5-10 ms) and interrupt-aggregation logic. The 0-70 C commercial range fits standard factory enclosures, and the ceramic package survives industrial vibration.
Recommandé
Legacy Printer and Plotter Controller Logic
The EP1810JC35 is found inside late-1980s to mid-1990s HP LaserJet, Epson dot-matrix and HP-GL plotters as the glue-logic hub linking the formatter ASIC to the print engine, paper-feed motors and operator panel. Its 48 macrocells consolidate stepper-direction control, sensor debouncing, and print-head strobe generation into one programmable device. For repair shops, the EP1810JC35 remains the only authorized replacement part and is supplied through legacy distributors as of 2026.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EP1810JC35 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EP1810JC-25 | EP1810JC-45 | EP1810GC-35 | EP1810GC-35AB | EP1810GI-45 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PLCC-68 (J-lead, ceramic) | PLCC-68 (J-lead, ceramic) - same | PLCC-68 (J-lead, ceramic) - same | PLCC-68 (J-lead, ceramic) - same | PLCC-68 (J-lead, ceramic) - same | PLCC-68 (J-lead, ceramic) - same |
| Macrocells | 48 | 48 | 48 | 48 | 48 | 48 |
| Propagation Delay (tPD) | 35 ns | 25 ns (28.6% faster) | 45 ns (28.6% slower) | 35 ns (identical) | 35 ns (identical) | 45 ns (28.6% slower) |
| Maximum Clock Frequency | 40 MHz | 50 MHz (estimated from tPD) | 30 MHz (estimated from tPD) | 40 MHz | 40 MHz | 30 MHz (estimated from tPD) |
| Supply Voltage (max VCC) | 5.25 V | 5.25 V | 5.25 V | 5.25 V | 5.25 V | 5.25 V |
| Operating Temperature | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial, AB screened) | -40 C to +85 C (Industrial) |
| Process Technology | CMOS EPROM | CMOS EPROM | CMOS EPROM | CMOS EPROM (windowed UV-erasable) | CMOS EPROM (windowed UV-erasable) | CMOS EPROM |
Principaux différenciateurs
- 35 ns speed grade is the cost-optimized middle of the Classic EP1810 family (vs EP1810JC-25)
- Commercial temperature grade is sufficient for industrial enclosure designs (vs EP1810GI-45)
- J-lead ceramic package supports high-reliability through-hole assembly (vs Plastic-leaded PLCC variant (LC suffix))
Notes de conception
Estimated: at 5 V VCC and 40 MHz toggle on 24 of 48 macrocells, the EP1810JC35 draws approximately 60-90 mA ICC. Place a 10 uF bulk tantalum capacitor at the PLCC-68 VCC pin (pin 68) and a 0.1 uF ceramic decoupling cap adjacent to every GND/VCC pair (pins 12/25/37/49/61). Without proper decoupling, simultaneous switching of multiple macrocells can inject VCC bounce of 200-400 mV that violates the 4.75 V minimum VCC spec.
Do not exceed 5.25 V on VCC - the EP1810JC35 is a 5 V CMOS EPROM device without 5 V tolerance margin and will suffer junction breakdown if a regulated 5.0 V rail sags upward during motor inrush events. Add a 5.1 V Zener clamp or LDO regulator between the raw bus and VCC for industrial applications. Also note that the device is one-time-programmable (OTP) unless the lid is a UV-transparent window, so verify the lid type before erasing during rework.
Route the four GND pins (12, 25, 37, 49, 61) to a continuous ground pour on the PLCC-68 socket footprint; do not daisy-chain GND through signal traces. Use a PLCC-68 through-hole socket (Augat or 3M Textool) during prototyping so windowed UV-erase variants can be reused; switch to direct solder for production. Keep clock-input traces shorter than 25 mm with 50 ohm controlled impedance to avoid ringing at 40 MHz.
Estimated: each macrocell output has approximately 25-35 pF of output capacitance in the Classic EPLD architecture, limiting simultaneous-switching-output count to about 8 outputs before edge-rate degradation exceeds 5 ns. Distribute high-frequency outputs across all four sides of the PLCC package to minimize ground bounce. For bus-driving applications above 16 MHz, buffer the EPLD outputs with 74F244 or 74ABT244 transceivers.
Informations de conformité
RoHS and lead-free status not stated in verified distributor data as of 2026-09-06. The EP1810JC35 is a 1990s-era commercial ceramic PLD originally manufactured before RoHS took effect in 2006; most lots are likely non-compliant. Verify compliance with the broker before placing orders for RoHS-restricted markets.
