EP1810JC-45 - Classic EPLD, 48 Macrocells, 45ns, UV PLCC | Altera
Référence : EP1810JC-45 ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $38.5 | $38,50 |
| 10 | $32.75 | $327,50 |
| 100 | $27.2 | $2 720,00 |
| 500 | $23.4 | $11 700,00 |
| 1 000 | $21.1 | $21 100,00 |
EP1810JC-45 Présentation
A Classic EPLD (Erasable Programmable Logic Device) is a one-time- or UV-erasable non-volatile logic device that predates modern SRAM-based FPGAs and flash-based CPLDs. In the system hierarchy it sits between discrete 74-series glue logic and modern FPGA/CPLD architectures: each macrocell contains a programmable AND/OR array plus a flip-flop, and the global/local buses fan logic between the AND array and the macrocell register bank. Because the device is non-volatile and instantly reconfigurable without external boot memory, Classic EPLDs were widely used for address decoding, bus arbitration, state-machine control, and glue logic in 1980s and 1990s designs.
Key features of the EP1810JC-45 include 48 macrocells, 12 dedicated inputs plus 48 bidirectional I/O lines for 60 total usable I/Os, a 33.3 MHz maximum clock frequency, and a 5.25 V maximum supply voltage with CMOS technology. The part is offered in a commercial temperature grade (typically 0C to 70C) and supports both synchronous and asynchronous logic designs via per-macrocell flip-flops with individual clear, preset, and output-enable control. Programming is performed via a standard Altera programming algorithm through the dedicated programming pins.
Typical applications for the EP1810JC-45 include microprocessor address decoding, DMA control logic, peripheral-chip glue logic in 8-bit and 16-bit systems, bus-interface adapters, and replacement of multiple 74LS/74ALS TTL packages. The 2100-gate capacity also makes it usable for small state machines, interrupt controllers, and timing/sequencer functions in legacy industrial controllers and test equipment.
When designing with this device, ensure that the supply voltage does not exceed 5.25 V and that high-speed signals use the dedicated fast-input pins rather than I/O pins. The windowed ceramic package allows repeated UV erasure, which is essential for prototype iteration - plan for a 30-60 minute UV erase cycle when iterating logic designs. The part is now in NRND/last-time-buy status at Altera/Intel, so long-term designs should consider modern MAX series replacements.
This page synthesizes distributor pricing, package-level compatibility notes, and drop-in alternatives that are not consolidated in any single manufacturer document.
Alternatives de remplacement direct pour EP1810JC-45 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EP1810JC-45 (même facteur de forme et même empreinte) — différant par Mounting Type, Operating Temperature, Technology, Package, Package Type.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EP1810JC-35
✅ Remplacement direct✓ En stock
$5.48 / unité
Voir la fiche technique →EP1810JC-25
✅ Remplacement direct✓ En stock
$6.8 / unité
Voir la fiche technique →EP1810GI-45
✅ Remplacement direct✓ En stock
$56.4 / unité
Voir la fiche technique →EP1810GM883B
✅ Remplacement direct✓ En stock
$125.4 / unité
Voir la fiche technique →EP1810GC-35AB
✅ Remplacement direct✓ En stock
$9.95 / unité
Voir la fiche technique →EP1810GC-35
✅ Remplacement direct✓ En stock
$177.12 / unité
Voir la fiche technique →EP1810JC-45 Valeurs maximales et caractéristiques électriques
| Product Type | Classic EPLD (Erasable Programmable Logic Device) |
| Family | EP1810 (Classic EPLD Family) |
| Macrocells | 48 |
| Equivalent Gates | 2100 gates |
| Dedicated Inputs | 12 |
| I/O Pins | 48 |
| Total User I/O | 60 |
| Propagation Delay (tpd) | 45 ns |
| Fréquence d'horloge maximale | 33.3 MHz |
| Technology | CMOS, UV-erasable |
| Maximum Supply Voltage | 5.25 V |
| Boîtier | PLCC-68 (QCCJ, J-Lead, windowed ceramic) |
| Nombre de broches | 68 |
| Package Code | QCCJ |
| Temperature Grade | Commercial |
| Type de montage | Surface Mount |
Configuration des broches de EP1810JC-45
| Broche 1 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 2 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 3 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 4 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 5 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 6 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 7 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 8 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 9 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 10 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 11 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 12 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 13 | GND — Ground |
| Broche 14 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 15 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 16 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 17 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 18 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 19 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 20 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 21 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 22 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 23 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 24 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 25 | GND — Ground |
| Broche 26 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 27 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 28 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 29 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 30 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 31 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 32 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 33 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 34 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 35 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 36 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 37 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 38 | GND — Ground |
| Broche 39 | IN — Dedicated input pin |
| Broche 40 | IN — Dedicated input pin |
| Broche 41 | IN — Dedicated input pin |
| Broche 42 | IN — Dedicated input pin |
| Broche 43 | IN — Dedicated input pin |
| Broche 44 | IN — Dedicated input pin |
| Broche 45 | IN — Dedicated input pin |
| Broche 46 | IN — Dedicated input pin |
| Broche 47 | IN — Dedicated input pin |
| Broche 48 | IN — Dedicated input pin |
| Broche 49 | IN — Dedicated input pin |
| Broche 50 | GND — Ground |
| Broche 51 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 52 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 53 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 54 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 55 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 56 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 57 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 58 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 59 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 60 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 61 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 62 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 63 | GND — Ground |
| Broche 64 | VCC — Power supply (5 V typical) |
| Broche 65 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 66 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 67 | I/O — Bidirectional I/O pin (macrocell I/O) |
| Broche 68 | I/O — Bidirectional I/O pin (macrocell I/O) |
Applications typiques
EP1810JC-45 convient pour 6 applications: Microprocessor Address Decoding, Bus Arbitration and DMA Control Logic, Peripheral Chip Glue Logic Replacement, Industrial Control State Machines, Legacy Test and Measurement Equipment, Telecommunications Interface Adapters.
Microprocessor Address Decoding
The EP1810JC-45's 48 macrocells and 12 dedicated fast inputs make it well-suited for microprocessor address decoding in 8-bit and 16-bit systems. With 2100 equivalent gates of capacity, the device can implement full 16-bit or 24-bit address decoders with chip-select outputs for ROM, RAM, and peripheral memory maps. The 45 ns tpd is fast enough for decode insertion in systems with clock frequencies up to ~15 MHz (with derating), and the UV-erasable ceramic package allows prototype iteration when refining memory maps during development.
Recommandé
Bus Arbitration and DMA Control Logic
Bus arbitration and DMA control logic benefit from the EP1810JC-45's 48 bidirectional I/O pins and dedicated flip-flops in each macrocell. The device can implement multi-master bus arbiters, HOLD/HLTA sequences, and DMA controller state machines that replace 4-6 discrete 74LS/ALS TTL packages per function. The 5 V CMOS technology matches TTL logic levels directly, eliminating level translators. The windowed ceramic package supports prototype iteration of arbitration algorithms before committing to a non-windowed production part.
Recommandé
Peripheral Chip Glue Logic Replacement
The EP1810JC-45 can replace entire boards of 74LS/74ALS glue logic in peripheral and interface cards. A single EP1810 implements 4-8 standard MSI functions (decoders, multiplexers, latches, parity generators) in one package, reducing board area by 60-70% and improving noise margins through lower aggregate switching current. The 33.3 MHz maximum clock frequency supports ISA bus and similar peripheral bus timings. Designers migrating legacy 74-series logic to a single EPLD gain PCB simplification and improved reliability.
Recommandé
Industrial Control State Machines
Industrial controllers and machine automation systems use the EP1810JC-45 for state-machine control of conveyor sequencers, packaging machinery, and process controllers. Each macrocell provides a dedicated flip-flop with clear/preset control, ideal for Mealy and Moore state machines. The 2100-gate capacity supports 16-32 state FSMs with 4-8 output actions. The 5 V supply and CMOS technology provide good noise immunity for factory-floor environments, though industrial-grade EP1810GI-45 is preferred for -40C to +85C operation.
Recommandé
Legacy Test and Measurement Equipment
Test and measurement instruments with EP1810JC-45 logic include timing generators, frequency counters, and protocol analyzers built in the 1990s. The device's deterministic 45 ns tpd makes it useful for precise timing circuits where CPLD/FPGA jitter would be unacceptable. Maintenance and repair of legacy T&M equipment is the primary current use case - the UV-erasable windowed ceramic package supports in-house reprogramming when logic updates are needed during service.
Recommandé
Telecommunications Interface Adapters
The EP1810JC-45 was widely used in telecommunications equipment for serial-interface adapters, T1/E1 framer glue logic, and X.25 protocol controllers. The 5 V CMOS technology directly interfaces with TTL-level telecom bus standards, and the 48 I/Os handle multiple serial channels plus control/status signaling. For legacy telecom systems still in service, the EP1810JC-45 provides proven reliability and field-validated operation, though new designs should migrate to modern MAX V or Lattice ispMACH CPLDs.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EP1810JC-45 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EP1810JC-35 | EP1810JC-25 | EP1810GI-45 | EP1810GM883B | EP1810GC-35AB | EP1810GC-35 |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | PLCC-68 (QCCJ) | PLCC-68 (QCCJ) - same | PLCC-68 (QCCJ) - same | PLCC-68 (QCCJ) - same | PLCC-68 (QCCJ) - same | PLCC-68 (QCCJ) - same | PLCC-68 (QCCJ) - same |
| Propagation Delay (tpd) | 45 ns | 35 ns (-22%) | 25 ns (-44%) | 45 ns (same) | 45 ns (same) | 35 ns (-22%) | 35 ns (-22%) |
| Macrocells | 48 | 48 (same) | 48 (same) | 48 (same) | 48 (same) | 48 (same) | 48 (same) |
| Max Clock Frequency | 33.3 MHz | 33.3 MHz | 33.3 MHz | 33.3 MHz | 33.3 MHz | 33.3 MHz | 33.3 MHz |
| Temperature Grade | Commercial | Commercial | Commercial | Industrial (-40C to +85C) | Military (MIL-STD-883B) | Commercial | Commercial |
| Package Type | Windowed ceramic (UV-erasable) | Windowed ceramic (UV-erasable) | Windowed ceramic (UV-erasable) | Windowed ceramic (UV-erasable) | Windowed ceramic (UV-erasable) | Plastic non-windowed (one-time-programmable) | Plastic non-windowed (one-time-programmable) |
| Supply Voltage Max | 5.25 V | 5.25 V | 5.25 V | 5.25 V | 5.25 V | 5.25 V | 5.25 V |
Principaux différenciateurs
- Speed grade position in EP1810 family (vs EP1810JC-35)
- Windowed ceramic vs plastic package (vs EP1810GC-35)
- Commercial vs industrial temperature grade (vs EP1810GI-45)
Notes de conception
The EP1810JC-45 operates from a single 5 V supply (4.5 V to 5.25 V range) with CMOS technology. Decouple VCC with a 0.1 uF ceramic capacitor placed within 5 mm of the VCC pin, plus a 10 uF tantalum bulk capacitor at the board power-entry point. Estimated: at 33.3 MHz with all 48 I/Os switching, dynamic current is approximately 30-50 mA. The four GND pins (13, 25, 38, 50) must all be connected for proper operation.
Do not confuse EP1810JC-45 (ceramic windowed, UV-erasable, prototyping) with EP1810GC-45 (plastic, one-time-programmable, production). Both share the PLCC-68 footprint but only the JC variant supports UV erasure for logic iteration. Also note: Classic EPLDs require a specific programming algorithm via dedicated programming pins - they cannot be programmed in-circuit like modern flash CPLDs.
The windowed ceramic QCCJ package has limited thermal dissipation - at 33.3 MHz with full I/O switching, the device dissipates approximately 250-400 mW. Commercial temperature grade (0C to 70C) is standard. For higher temperature or vibration environments, consider the EP1810GI-45 (industrial, -40C to +85C) or EP1810GM883B (MIL-STD-883 screened).
Place the EP1810JC-45 with pin 1 orientation matching the PLCC-68 socket orientation. Use a machined-pin PLCC socket (not the cheaper stamped sockets) for reliable prototyping cycles - the J-lead ceramic package contacts wear with repeated insertion. For UV erasure, ensure at least 25 mm of clearance above the quartz window for the UV eraser lamp.
Informations de conformité
EP1810 family datasheet (1989) predates RoHS compliance documentation. RoHS/REACH status not stated in verified data - assume non-compliant for the original ceramic JC variant. The plastic GC variants may have later RoHS-compliant revisions; verify with the actual manufacturer before use in RoHS-required designs. AEC-Q100 not applicable - this is a commercial/industrial/military logic device.
