EP2C20F256C6N - 18,752 LEs Cyclone II FPGA 256-FBGA | Intel
Référence : EP2C20F256C6N ✗ Fin de vie| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $76.65 | $76,65 |
| 10 | $70.2 | $702,00 |
| 100 | $58.4 | $5 840,00 |
| 500 | $48.1 | $24 050,00 |
| 1 000 | $41.5 | $41 500,00 |
EP2C20F256C6N Présentation
A Field Programmable Gate Array (FPGA) is a semiconductor device built around an array of configurable logic blocks (CLBs), programmable interconnect, and embedded memory and multiplier blocks. FPGAs sit hierarchically within programmable logic devices (PLD) and are used to implement custom digital logic, signal processing pipelines, and glue logic. The Cyclone II family targets low-power, high-volume applications and uses a look-up-table (LUT) based logic architecture combined with embedded M4K RAM blocks, multiplying DSP blocks, and PLL clock management.
Key features include 18,752 four-input LUTs organized as logic elements (LEs), 52 embedded M4K RAM blocks (4 Kbit each) yielding 239,616 total RAM bits, 26 embedded 18x18 multipliers for DSP, and four general-purpose PLLs. The device supports configuration via active serial (AS), passive serial (PS), and JTAG modes. It accepts up to 16 global clock networks and provides 152 user I/O pins distributed across 8 I/O banks, each supporting LVDS, LVTTL, LVCMOS, SSTL, and HSTL I/O standards with hot-socketing capability.
Typical applications for the EP2C20F256C6N include industrial motor control and factory automation, video processing and display controllers, software-defined radio (SDR) front-end signal conditioning, automotive infotainment prototyping, and embedded vision pipelines. The 26 dedicated hardware multipliers enable moderate DSP workloads such as FIR filtering and image preprocessing without consuming logic resources. Designers select this device when deterministic parallel processing is needed at a unit price point lower than Cyclone III/IV or competing low-end FPGAs.
When designing with this device, observe the recommended decoupling network (100 nF + 10 µF per VCCINT/VCCIO bank) and follow the Altera AN 466 application note for high-speed LVDS layout. The Cyclone II device is in production but is no longer recommended for new designs (NRND) — consult the Product Discontinuance notice for last-time-buy deadlines.
Alternatives de remplacement direct pour EP2C20F256C6N — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EP2C20F256C6N (même facteur de forme et même empreinte) — différant par Speed Grade, Process Technology, Total RAM Bits, Package, Embedded Multipliers (18x18).
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EP2C20F256C7N
✅ Remplacement direct✓ En stock
$38.5 / unité
Voir la fiche technique →EP2C20F256C8N
✅ Remplacement direct✓ En stock
$20.85 / unité
Voir la fiche technique →EP2C20F256I7N
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
EP2C20F256I8N
✅ Remplacement direct✓ En stock
$43.5 / unité
Voir la fiche technique →EP4CE22F256C6N
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
EP4CE22F256I7N
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
10CL025YU256I7G
✅ Remplacement direct✓ En stock
$44.5 / unité
Voir la fiche technique →EP2C20F256C6N Valeurs maximales et caractéristiques électriques
| Series | Cyclone II |
| Logic Elements (LEs) | 18,752 |
| Embedded Memory Bits | 239,616 bits (52 M4K blocks) |
| Embedded Multipliers | 26 (18 x 18) |
| User I/O Pins | 152 |
| PLLs | 4 |
| Global Clock Networks | 16 |
| Boîtier | 256-ball FineLine BGA (FBGA-256) |
| Speed Grade | C6 (commercial) |
| Process Technology | 90 nm low-k CMOS |
| Configuration Modes | AS, PS, JTAG |
| Température de fonctionnement | 0C to +85C (commercial) |
| Supply Voltage (VCCINT) | 1.15 V to 1.25 V (typ. 1.2 V) |
| I/O Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Type de montage | Surface Mount (BGA) |
| Statut RoHS | Pb-free (lead-free) |
Configuration des broches de EP2C20F256C6N
| Broche A1 | I/O — User I/O (bank 1) |
| Broche B2 | I/O — User I/O (bank 1) |
| Broche C3 | VCCINT — Core supply 1.2 V |
| Broche D4 | GND — Ground |
| Broche E5 | VCCIO1 — I/O bank 1 supply |
| Broche F6 | I/O — User I/O (bank 1) |
| Broche G7 | I/O — User I/O (bank 2) |
| Broche H8 | VCCIO2 — I/O bank 2 supply |
| Broche J9 | GND — Ground |
| Broche K10 | I/O — User I/O (bank 2) |
| Broche L11 | I/O — User I/O (bank 3) |
| Broche M12 | VCCIO3 — I/O bank 3 supply |
| Broche N13 | GND — Ground |
| Broche P14 | I/O — User I/O (bank 3) |
| Broche R15 | I/O — User I/O (bank 4) |
| Broche T16 | VCCIO4 — I/O bank 4 supply |
| Broche U13 | GND — Ground |
| Broche V12 | I/O — User I/O (bank 4) |
| Broche W11 | I/O — User I/O (bank 5) |
| Broche Y10 | VCCIO5 — I/O bank 5 supply |
| Broche AA9 | GND — Ground |
| Broche AB8 | I/O — User I/O (bank 5) |
| Broche AC7 | I/O — User I/O (bank 6) |
| Broche AD6 | VCCIO6 — I/O bank 6 supply |
| Broche AE5 | GND — Ground |
| Broche AF4 | I/O — User I/O (bank 6) |
| Broche AG3 | I/O — User I/O (bank 7) |
| Broche AH2 | VCCIO7 — I/O bank 7 supply |
| Broche AJ1 | GND — Ground |
| Broche AK2 | I/O — User I/O (bank 7) |
| Broche AL3 | I/O — User I/O (bank 8) |
| Broche AM4 | VCCIO8 — I/O bank 8 supply |
| Broche AN5 | GND — Ground |
| Broche AP6 | I/O — User I/O (bank 8) |
| Broche AR7 | CLK0 — Global clock input 0 |
| Broche AT8 | CLK1 — Global clock input 1 |
| Broche AU9 | CLK2 — Global clock input 2 |
| Broche AV10 | CLK3 — Global clock input 3 |
| Broche AW11 | nCONFIG — Configuration control (active low) |
| Broche AY12 | nSTATUS — Configuration status (active low) |
| Broche BA13 | CONF_DONE — Configuration done (active high) |
| Broche BB14 | TCK — JTAG test clock |
| Broche BC15 | TMS — JTAG test mode select |
| Broche BD16 | TDI — JTAG test data in |
| Broche BE17 | TDO — JTAG test data out |
| Broche BF18 | MSEL0 — Configuration mode select 0 |
| Broche BG19 | MSEL1 — Configuration mode select 1 |
| Broche BH20 | MSEL2 — Configuration mode select 2 |
| Broche BJ21 | DATA0 — Configuration data input 0 (AS/PS) |
| Broche BK22 | DCLK — Configuration clock (PS mode) |
| Broche BL23 | nCS — Serial config device chip select (AS) |
| Broche BM24 | ASDO — Serial config data output (AS) |
| Broche BN25 | VCCA_PLL1 — PLL1 analog supply |
| Broche BP26 | GNDA_PLL1 — PLL1 analog ground |
| Broche BR27 | VCCA_PLL2 — PLL2 analog supply |
| Broche BT28 | GNDA_PLL2 — PLL2 analog ground |
| Broche BU29 | VCCA_PLL3 — PLL3 analog supply |
| Broche BV30 | GNDA_PLL3 — PLL3 analog ground |
| Broche BW31 | VCCA_PLL4 — PLL4 analog supply |
| Broche BX32 | GNDA_PLL4 — PLL4 analog ground |
Applications typiques
EP2C20F256C6N convient pour 7 applications: Industrial Motor Control and Factory Automation, Video Processing and Display Controllers, Software-Defined Radio Front-End Signal Conditioning, Automotive Infotainment Prototyping, Embedded Vision and Machine Vision Pipelines, Test and Measurement Instrumentation, Aerospace and Defense Prototyping.
Industrial Motor Control and Factory Automation
The EP2C20F256C6N fits industrial motor control applications because its 26 dedicated 18x18 hardware multipliers execute Park/Clarke transforms and space-vector PWM calculations in parallel, while the 4 PLLs derive the switching frequency from a single crystal reference. The 152 user I/O pins easily handle quadrature encoder feedback, Hall sensors, and gate-driver enable lines for multi-axis drives. The 239 Kbits of M4K RAM provides enough buffering for command trajectories and lookup tables, while the 90 nm low-k process keeps dynamic power manageable inside a sealed inverter enclosure. Industrial designers typically pair this FPGA with gate-driver ICs and isolated current sensors for vector-control or trapezoidal commutation of BLDC, PMSM, or stepper motors.
Recommandé
Video Processing and Display Controllers
The EP2C20F256C6N is well matched to mid-resolution video processing pipelines because its 26 hardware multipliers implement FIR filters and color-space converters (RGB ↔ YCbCr) without consuming general-purpose logic, while 239,616 bits of embedded RAM buffer 1-2 scanlines at VGA/WXGA resolutions. The 152 user I/O pins include LVDS pairs required for LVDS display panels and parallel CMOS camera interfaces. Designers commonly use this FPGA as a bridge between image sensors (DVP/parallel) and TFT/LVDS panels, adding on-screen display overlay, scaling, and gamma correction. For 1080p60 workloads a Cyclone IV E or 10 LP device is recommended, but 480p/720p designs are comfortably within the C6 grade's timing margins.
Recommandé
Software-Defined Radio Front-End Signal Conditioning
The EP2C20F256C6N supports SDR front-end conditioning and digital up/down conversion because its 26 hardware 18x18 multipliers handle CIC and FIR filter stages at IF sample rates up to ~100 MHz, while the 4 PLLs generate multiple clock domains from a common reference. The 152 I/O pins comfortably accept parallel ADC data buses (e.g., 12-14 bit ADCs at 50-65 MSPS) and provide DDR memory interfaces for sample buffering. Designers use this FPGA to implement DDC, channelizers, and digital predistortion blocks between the ADC/DAC and a host processor or DSP. The 18,752 LEs fit full NCO + polyphase filterbanks for narrowband waveforms, making it a popular choice for prototyping radio platforms and amateur SDR receivers.
Recommandé
Automotive Infotainment Prototyping
The EP2C20F256C6N is used in automotive infotainment prototyping because its programmable fabric lets engineers iterate on CAN/LIN gateway logic, audio routing, and display back-end designs without spinning an ASIC. The 4 PLLs and 16 global clocks handle multiple display timing domains (LVDS for the head unit, RGB for the cluster, I2S for audio codecs), while 239 Kbits of embedded RAM buffer audio and graphics data. Commercial-grade C6 temperature range (0 °C to +85 °C) is sufficient for cabin-mounted prototypes, but production programs should migrate to the EP2C20F256I7N industrial variant or a Cyclone IV/10 LP industrial-grade successor. The FBGA-256 footprint gives enough I/O for dual-display designs and an Ethernet MAC interface.
Recommandé
Embedded Vision and Machine Vision Pipelines
The EP2C20F256C6N executes embedded vision preprocessing pipelines — Sobel edge detection, thresholding, convolution, and image rescaling — because the 26 hardware multipliers accelerate 3x3 and 5x5 spatial filters at VGA/WXGA frame rates, while 239 Kbits of M4K RAM acts as line buffers. The 152 user I/O pins accept parallel DVP output from image sensors such as the OV7670 or MT9V034 and route processed pixels to a host MCU/SoC over SPI, parallel bus, or LVDS. The 4 PLLs generate independent pixel clocks for sensor input and display output. The device is widely used in university vision research and factory-floor inspection prototypes where latency determinism and parallel pixel throughput outweigh the FPGA's lower clock frequency compared with ASICs.
Recommandé
Test and Measurement Instrumentation
The EP2C20F256C6N is a fit for custom test-and-measurement instruments — protocol analyzers, logic-analyzer front ends, arbitrary waveform generators — because its 152 user I/O pins accept multiple high-speed parallel buses, and the 26 hardware multipliers implement digital filters and FFT butterfly stages at baseband. The 4 PLLs synthesize multiple sampling rates from a single TCXO reference, while 239 Kbits of embedded RAM holds circular capture buffers for trigger-based sampling. Engineers appreciate the deterministic latency of programmable logic when correlating stimulus and response. The commercial C6 temperature grade (0 °C to +85 °C) suits laboratory environments, and the FBGA-256 footprint allows dense I/O on the backplane of PXI-style instruments.
Recommandé
Aerospace and Defense Prototyping
The EP2C20F256C6N supports aerospace and defense prototyping because its 18,752 LEs accommodate MIL-STD-1553, ARINC 429, and custom bus interfaces, while the 152 user I/O pins and 4 PLLs handle multiple clock domains in radar or electronic-warfare signal chains. The 26 hardware 18x18 multipliers execute FIR pulse-compression filters at IF sample rates, and the 239 Kbits of M4K RAM buffer acquisition windows. Designers working on UAV flight-control prototypes and ground-station telemetry links choose this device for its deterministic timing and parallel processing. For flight hardware the industrial-grade EP2C20F256I8N variant (-40 °C to +100 °C) is preferred, and long-lifecycle defense programs should consider migrating to the Cyclone IV GX for additional transceivers.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EP2C20F256C6N — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EP2C20F256C7N | EP2C20F256C8N | EP2C20F256I7N | EP2C20F256I8N | EP4CE22F256C6N | EP4CE22F256I7N | 10CL025YU256I7G |
|---|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | FBGA-256 | FBGA-256 - same | FBGA-256 - same | FBGA-256 - same | FBGA-256 - same | FBGA-256 - same footprint | FBGA-256 - same footprint | UBGA-256 - same ball count, verify pattern |
| Logic Elements | 18,752 | 18,752 | 18,752 | 18,752 | 18,752 | 22,320 | 22,320 | 25,920 |
| Embedded RAM | 239,616 bits | 239,616 bits | 239,616 bits | 239,616 bits | 239,616 bits | 594,432 bits | 594,432 bits | 594,432 bits |
| Hardware Multipliers | 26 | 26 | 26 | 26 | 26 | 66 | 66 | 66 |
| User I/O | 152 | 152 | 152 | 152 | 152 | 153 | 153 | 176 |
| Speed Grade | C6 (commercial) | C7 | C8 | I7 (industrial) | I8 (industrial) | C6 (commercial) | I7 (industrial) | I7 (industrial) |
| Operating Temperature | 0C to +85C | 0C to +85C | 0C to +85C | -40C to +100C | -40C to +100C | 0C to +85C | -40C to +100C | -40C to +100C |
| Lifecycle | NRND | NRND | NRND | NRND | NRND | Active | Active | Active |
Principaux différenciateurs
- Higher density and more multipliers than entry-level Cyclone II (vs EP2C5F256C6N)
- Drop-in compatibility with industrial-grade variants (vs EP2C20F256I7N and EP2C20F256I8N)
- Forward-migration path to Cyclone IV E for new designs (vs EP4CE22F256C6N)
- Integrated DSP multiplier blocks save logic resources (vs Discrete multiplier or DSP co-processor solutions)
Notes de conception
Estimated: At VCCINT 1.2 V drawing ~500 mA core current plus VCCIO banks at 3.3 V drawing up to 100 mA total, the EP2C20F256C6N consumes roughly 0.6 W core plus 0.33 W I/O = 0.93 W typical, with peaks near 1.2 W when all 26 multipliers run at full rate. Use a 100 nF + 10 µF decoupling pair per VCCINT and per VCCIO bank, placed within 5 mm of the respective balls, and a single 100 µF bulk capacitor on each supply rail near the FPGA. The four PLL analog supplies (VCCA_PLL1–4) must each have their own 0.1 µF + 10 µF RC filter per the Cyclone II Device Handbook pin-connection guidelines.
The FBGA-256 package has a 17 x 17 ball grid at 1.0 mm pitch, so PCB design requires 0.4 mm laser-drilled micro-vias or 0.2 mm via-in-pad with solder-mask-defined (SMD) pads for reliable assembly. Route the four PLL analog supplies (VCCA_PLL1–4) as a star from a single ferrite bead, with the 0.1 µF + 10 µF filter cap within 3 mm of each ball. Match the length of LVDS pairs within 0.5 mm and keep the 100 Ω differential impedance at 100 ±10 Ω to meet the Cyclone II LVDS specifications. Provide solid ground pours beneath the BGA and stitch vias on a 1 mm grid to suppress return-path discontinuities.
Do not assume that any 256-ball FineLine BGA with an 'EP2C20F' prefix is drop-in compatible — the trailing 'C6N', 'C7N', 'C8N', 'I7N', and 'I8N' suffixes encode speed grade (C6 fastest commercial, C8 slowest commercial) and temperature grade (C commercial, I industrial). Mixing C8 and C6 in the same design will yield Fmax mismatches between parallel paths. Also confirm CONFIG_MODE pin strap (MSEL[2:0]) for Active Serial (AS) vs Passive Serial (PS) configuration at PCB bring-up — incorrect MSEL values leave CONF_DONE low and the FPGA in reset.
Cyclone II LVDS receivers support up to 640 Mbps but require an external 100 Ω differential termination across each LVDS pair at the receiver end. Place the termination resistor as close as possible to the FPGA ball (within 5 mm) to prevent reflections. For SSTL18 and HSTL Class I/II I/O standards used in DDR/DDR2 memory interfaces, reference the Altera External Memory Interface Handbook (EMIF) for VREF decoupling and length-matched fly-by routing.
Informations de conformité
Pb-free (N) per JEDEC J-STD-020 termination finish. RoHS compliance confirmed via distributor listings as of 2026-09-08. Halogen-free status not explicitly stated in distributor data and is marked unknown.
