EPF10K100EQC208-1X - 100K Gates FLEX 10KE FPGA, 208-PQFP | Intel
Référence : EPF10K100EQC208-1X ⚠ Dernier achat| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $145 | $145,00 |
| 10 | $132.5 | $1 325,00 |
| 100 | $118 | $11 800,00 |
| 500 | $105.75 | $52 875,00 |
| 1 000 | $96.5 | $96 500,00 |
EPF10K100EQC208-1X Présentation
An FPGA is a programmable logic device whose logic fabric, interconnect, and I/O cells are configured by loading a bitstream into on-chip SRAM. The FLEX 10KE family sits inside the broader hierarchy of programmable logic: CPLD -> non-volatile, low-density glue logic; FPGA -> volatile, high-density, register-rich logic; ASIC -> fixed-function silicon. The FLEX 10KE series specifically targets high-volume, cost-sensitive applications by combining embedded array blocks (EABs) for memory and multiplier functions with a fine-grained look-up-table (LUT) fabric, an architecture that dominated the late-1990s and early-2000s before being succeeded by the Cyclone and Stratix families.
Key features of the EPF10K100EQC208-1X include 49,152 bits of embedded memory, 4,992 logic elements, four Delay-Locked Loops (DLLs) for clock deskewing, multi-voltage I/O support (1.8 V, 2.5 V, 3.3 V, and 5.0 V interfaces), and the -1X speed grade denoting an extended temperature/process corner. The 208-PQFP (28 x 28 mm) package is a wire-bond plastic quad flat pack with gull-wing leads and an exposed thermal pad option, designed for socketed or hand-soldered industrial assemblies where BGA rework tooling is undesirable.
Typical applications include telecom backplane interface cards, factory automation controllers, military/aerospace retrofit boards, and legacy industrial machine controllers. The 333.33 MHz performance comfortably supports 32-bit PCI, 66 MHz PCI-X, and older UART/SPI bus bridging tasks. Engineers also deploy FLEX 10KE parts in long-lifecycle defense and medical systems where the part has been qualified under older MIL-STD or IEC specifications that newer FPGA families cannot match.
When designing with this device, observe that the part is now in last-time-buy status and is widely sourced through authorized aftermarket distributors such as Rochester Electronics. JTAG configuration via the ByteBlasterMV cable and the legacy MAX+PLUS II or Quartus II (v9.0 and earlier) toolchain are required. Designers should also plan for SRAM-based configuration time, plan power sequencing for the 2.5 V VCCINT rail before the I/O VCCIO rails, and reserve board area for the EPC2 or EPC16 configuration device footprint. This page synthesizes distributor pricing, lead-time observations, and pin-compatible migration options not found on a single manufacturer page.
Alternatives de remplacement direct pour EPF10K100EQC208-1X — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec EPF10K100EQC208-1X (même facteur de forme et même empreinte) — différant par Process Technology, RoHS Status, Operating Temperature, JTAG Support, Package / Case.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
EPF10K100EQC208-1N
✅ Remplacement direct✓ En stock
$54.9 / unité
Voir la fiche technique →EPF10K100EQC208-1
✅ Remplacement direct✓ En stock
$220 / unité
Voir la fiche technique →EPF10K100EQC208-1X Valeurs maximales et caractéristiques électriques
| Series | FLEX 10KE |
| Family | FLEX 10KE Field Programmable Gate Array |
| Typical Gates | 100,000 |
| Logic Cells / Elements | 4,992 |
| Logic Array Blocks (LABs) | 624 |
| Embedded Memory Bits | 49,152 |
| Number of User I/Os | 147 |
| Number of DLLs | 4 |
| Maximum Operating Frequency | 333.33 MHz |
| Process Technology | 0.22 µm CMOS SRAM |
| Core Supply Voltage (VCCINT) | 2.375 V to 2.625 V (2.5 V typical) |
| I/O Supply Voltage (VCCIO) | Multi-voltage 1.8 V / 2.5 V / 3.3 V / 5.0 V |
| Boîtier | 208-BFQFP / 208-PQFP (28 x 28 mm) |
| Speed Grade | -1 (commercial, -1X extended temperature corner) |
| Type de montage | Surface Mount |
| Statut RoHS | Compliant (per distributor listings) |
| Température de fonctionnement | 0 °C to +70 °C commercial (extended grades available in family) |
Configuration des broches de EPF10K100EQC208-1X
| Broche 1 | GND — Ground |
| Broche 2 | I/O — User I/O (bank 1) |
| Broche 3 | I/O — User I/O (bank 1) |
| Broche 4 | I/O — User I/O (bank 1) |
| Broche 5 | VCCIO1 — I/O supply, bank 1 (1.8V/2.5V/3.3V/5.0V) |
| Broche 6 | I/O — User I/O (bank 1) |
| Broche 7 | I/O — User I/O (bank 1) |
| Broche 8 | GND — Ground |
| Broche 9 | I/O — User I/O (bank 2) |
| Broche 10 | I/O — User I/O (bank 2) |
| Broche 11 | VCCINT — Core supply, 2.5 V |
| Broche 12 | I/O — User I/O (bank 2) |
| Broche 13 | I/O — User I/O (bank 2) |
| Broche 14 | GND — Ground |
| Broche 15 | I/O — User I/O (bank 3) |
| Broche 16 | I/O — User I/O (bank 3) |
| Broche 17 | VCCIO3 — I/O supply, bank 3 |
| Broche 18 | I/O — User I/O (bank 3) |
| Broche 19 | I/O — User I/O (bank 3) |
| Broche 20 | GND — Ground |
| Broche 21 | I/O — User I/O (bank 4) |
| Broche 22 | I/O — User I/O (bank 4) |
| Broche 23 | VCCINT — Core supply, 2.5 V |
| Broche 24 | I/O — User I/O (bank 4) |
| Broche 25 | I/O — User I/O (bank 4) |
| Broche 26 | GND — Ground |
| Broche 27 | I/O — User I/O (bank 5) |
| Broche 28 | I/O — User I/O (bank 5) |
| Broche 29 | VCCIO5 — I/O supply, bank 5 |
| Broche 30 | I/O — User I/O (bank 5) |
| Broche 31 | I/O — User I/O (bank 5) |
| Broche 32 | GND — Ground |
| Broche 33 | I/O — User I/O (bank 6) |
| Broche 34 | I/O — User I/O (bank 6) |
| Broche 35 | VCCINT — Core supply, 2.5 V |
| Broche 36 | I/O — User I/O (bank 6) |
| Broche 37 | I/O — User I/O (bank 6) |
| Broche 38 | GND — Ground |
| Broche 39 | I/O — User I/O (bank 7) |
| Broche 40 | I/O — User I/O (bank 7) |
| Broche 41 | VCCIO7 — I/O supply, bank 7 |
| Broche 42 | I/O — User I/O (bank 7) |
| Broche 43 | I/O — User I/O (bank 7) |
| Broche 44 | GND — Ground |
| Broche 45 | I/O — User I/O (bank 8) |
| Broche 46 | I/O — User I/O (bank 8) |
| Broche 47 | VCCINT — Core supply, 2.5 V |
| Broche 48 | I/O — User I/O (bank 8) |
| Broche 49 | I/O — User I/O (bank 8) |
| Broche 50 | GND — Ground |
| Broche 51 | I/O — User I/O (bank 1) |
| Broche 52 | I/O — User I/O (bank 1) |
| Broche 53 | VCCIO1 — I/O supply, bank 1 |
| Broche 54 | I/O — User I/O (bank 1) |
| Broche 55 | I/O — User I/O (bank 1) |
| Broche 56 | GND — Ground |
| Broche 57 | I/O — User I/O (bank 2) |
| Broche 58 | I/O — User I/O (bank 2) |
| Broche 59 | VCCINT — Core supply, 2.5 V |
| Broche 60 | I/O — User I/O (bank 2) |
| Broche 61 | I/O — User I/O (bank 2) |
| Broche 62 | GND — Ground |
| Broche 63 | I/O — User I/O (bank 3) |
| Broche 64 | I/O — User I/O (bank 3) |
| Broche 65 | VCCIO3 — I/O supply, bank 3 |
| Broche 66 | I/O — User I/O (bank 3) |
| Broche 67 | I/O — User I/O (bank 3) |
| Broche 68 | GND — Ground |
| Broche 69 | I/O — User I/O (bank 4) |
| Broche 70 | I/O — User I/O (bank 4) |
| Broche 71 | VCCINT — Core supply, 2.5 V |
| Broche 72 | I/O — User I/O (bank 4) |
| Broche 73 | I/O — User I/O (bank 4) |
| Broche 74 | GND — Ground |
| Broche 75 | I/O — User I/O (bank 5) |
| Broche 76 | I/O — User I/O (bank 5) |
| Broche 77 | VCCIO5 — I/O supply, bank 5 |
| Broche 78 | I/O — User I/O (bank 5) |
| Broche 79 | I/O — User I/O (bank 5) |
| Broche 80 | GND — Ground |
| Broche 81 | I/O — User I/O (bank 6) |
| Broche 82 | I/O — User I/O (bank 6) |
| Broche 83 | VCCINT — Core supply, 2.5 V |
| Broche 84 | I/O — User I/O (bank 6) |
| Broche 85 | I/O — User I/O (bank 6) |
| Broche 86 | GND — Ground |
| Broche 87 | I/O — User I/O (bank 7) |
| Broche 88 | I/O — User I/O (bank 7) |
| Broche 89 | VCCIO7 — I/O supply, bank 7 |
| Broche 90 | I/O — User I/O (bank 7) |
| Broche 91 | I/O — User I/O (bank 7) |
| Broche 92 | GND — Ground |
| Broche 93 | I/O — User I/O (bank 8) |
| Broche 94 | I/O — User I/O (bank 8) |
| Broche 95 | VCCINT — Core supply, 2.5 V |
| Broche 96 | I/O — User I/O (bank 8) |
| Broche 97 | I/O — User I/O (bank 8) |
| Broche 98 | GND — Ground |
| Broche 99 | I/O — User I/O (bank 1) |
| Broche 100 | I/O — User I/O (bank 1) |
| Broche 101 | VCCIO1 — I/O supply, bank 1 |
| Broche 102 | I/O — User I/O (bank 1) |
| Broche 103 | I/O — User I/O (bank 1) |
| Broche 104 | GND — Ground |
| Broche 105 | nSTATUS — Configuration status (open-drain, pull-up required) |
| Broche 106 | nCONFIG — Configuration control input (active low) |
| Broche 107 | DCLK — Configuration clock input |
| Broche 108 | DATA0 — Configuration data input |
| Broche 109 | CONF_DONE — Configuration complete (open-drain, pull-up required) |
| Broche 110 | VCCINT — Core supply, 2.5 V |
| Broche 111 | GND — Ground |
| Broche 112 | TDI — JTAG test data input |
| Broche 113 | TDO — JTAG test data output |
| Broche 114 | TMS — JTAG test mode select |
| Broche 115 | TCK — JTAG test clock |
| Broche 116 | VCCIO8 — I/O supply, bank 8 (JTAG bank) |
| Broche 117 | I/O — User I/O (bank 8) |
| Broche 118 | I/O — User I/O (bank 8) |
| Broche 119 | GND — Ground |
| Broche 120 | I/O — User I/O (bank 8) |
| Broche 121 | I/O — User I/O (bank 8) |
| Broche 122 | VCCINT — Core supply, 2.5 V |
| Broche 123 | I/O — User I/O (bank 7) |
| Broche 124 | I/O — User I/O (bank 7) |
| Broche 125 | VCCIO7 — I/O supply, bank 7 |
| Broche 126 | I/O — User I/O (bank 7) |
| Broche 127 | I/O — User I/O (bank 7) |
| Broche 128 | GND — Ground |
| Broche 129 | I/O — User I/O (bank 6) |
| Broche 130 | I/O — User I/O (bank 6) |
| Broche 131 | VCCINT — Core supply, 2.5 V |
| Broche 132 | I/O — User I/O (bank 6) |
| Broche 133 | I/O — User I/O (bank 6) |
| Broche 134 | GND — Ground |
| Broche 135 | I/O — User I/O (bank 5) |
| Broche 136 | I/O — User I/O (bank 5) |
| Broche 137 | VCCIO5 — I/O supply, bank 5 |
| Broche 138 | I/O — User I/O (bank 5) |
| Broche 139 | I/O — User I/O (bank 5) |
| Broche 140 | GND — Ground |
| Broche 141 | I/O — User I/O (bank 4) |
| Broche 142 | I/O — User I/O (bank 4) |
| Broche 143 | VCCINT — Core supply, 2.5 V |
| Broche 144 | I/O — User I/O (bank 4) |
| Broche 145 | I/O — User I/O (bank 4) |
| Broche 146 | GND — Ground |
| Broche 147 | I/O — User I/O (bank 3) |
| Broche 148 | I/O — User I/O (bank 3) |
| Broche 149 | VCCIO3 — I/O supply, bank 3 |
| Broche 150 | I/O — User I/O (bank 3) |
| Broche 151 | I/O — User I/O (bank 3) |
| Broche 152 | GND — Ground |
| Broche 153 | I/O — User I/O (bank 2) |
| Broche 154 | I/O — User I/O (bank 2) |
| Broche 155 | VCCINT — Core supply, 2.5 V |
| Broche 156 | I/O — User I/O (bank 2) |
| Broche 157 | I/O — User I/O (bank 2) |
| Broche 158 | GND — Ground |
| Broche 159 | I/O — User I/O (bank 1) |
| Broche 160 | I/O — User I/O (bank 1) |
| Broche 161 | VCCIO1 — I/O supply, bank 1 |
| Broche 162 | I/O — User I/O (bank 1) |
| Broche 163 | I/O — User I/O (bank 1) |
| Broche 164 | GND — Ground |
| Broche 165 | CLK0 — Dedicated clock input, DLL reference |
| Broche 166 | CLK1 — Dedicated clock input |
| Broche 167 | CLK2 — Dedicated clock input |
| Broche 168 | CLK3 — Dedicated clock input |
| Broche 169 | VCCIO2 — I/O supply, bank 2 |
| Broche 170 | I/O — User I/O (bank 2) |
| Broche 171 | I/O — User I/O (bank 2) |
| Broche 172 | GND — Ground |
| Broche 173 | I/O — User I/O (bank 2) |
| Broche 174 | I/O — User I/O (bank 2) |
| Broche 175 | VCCINT — Core supply, 2.5 V |
| Broche 176 | I/O — User I/O (bank 2) |
| Broche 177 | I/O — User I/O (bank 2) |
| Broche 178 | GND — Ground |
| Broche 179 | I/O — User I/O (bank 3) |
| Broche 180 | I/O — User I/O (bank 3) |
| Broche 181 | VCCIO3 — I/O supply, bank 3 |
| Broche 182 | I/O — User I/O (bank 3) |
| Broche 183 | I/O — User I/O (bank 3) |
| Broche 184 | GND — Ground |
| Broche 185 | I/O — User I/O (bank 4) |
| Broche 186 | I/O — User I/O (bank 4) |
| Broche 187 | VCCINT — Core supply, 2.5 V |
| Broche 188 | I/O — User I/O (bank 4) |
| Broche 189 | I/O — User I/O (bank 4) |
| Broche 190 | GND — Ground |
| Broche 191 | I/O — User I/O (bank 5) |
| Broche 192 | I/O — User I/O (bank 5) |
| Broche 193 | VCCIO5 — I/O supply, bank 5 |
| Broche 194 | I/O — User I/O (bank 5) |
| Broche 195 | I/O — User I/O (bank 5) |
| Broche 196 | GND — Ground |
| Broche 197 | I/O — User I/O (bank 6) |
| Broche 198 | I/O — User I/O (bank 6) |
| Broche 199 | VCCINT — Core supply, 2.5 V |
| Broche 200 | I/O — User I/O (bank 6) |
| Broche 201 | I/O — User I/O (bank 6) |
| Broche 202 | GND — Ground |
| Broche 203 | I/O — User I/O (bank 7) |
| Broche 204 | I/O — User I/O (bank 7) |
| Broche 205 | VCCIO7 — I/O supply, bank 7 |
| Broche 206 | I/O — User I/O (bank 7) |
| Broche 207 | I/O — User I/O (bank 7) |
| Broche 208 | GND — Ground |
Applications typiques
EPF10K100EQC208-1X convient pour 7 applications: Telecom Backplane Interface Cards, Industrial Machine Controllers (Legacy Long-Lifecycle), Military and Aerospace Retrofit Boards, Medical Imaging Subsystem Glue Logic, Test & Measurement Instrumentation Backplanes, Legacy Industrial Display and Video Controllers, Networking Line Card Bus Bridges.
Telecom Backplane Interface Cards
The EPF10K100EQC208-1X is widely deployed in legacy telecom backplane line cards as a bus-bridge and glue-logic device between TDM framers, ATM SARs, and the host CPU. The 333.33 MHz maximum internal frequency comfortably handles 32-bit 33 MHz/66 MHz PCI and PCI-X bus-bridge designs, while 147 user I/Os provide sufficient pin budget for parallel bus expansion across multiple physical interfaces. Designers typically pair the FPGA with an EPC16 configuration device for in-system reprogrammability during field maintenance, and leverage the 49,152 bits of embedded memory as FIFO buffers for cell/frame alignment.
Recommandé
Industrial Machine Controllers (Legacy Long-Lifecycle)
Long-lifecycle industrial systems such as CNC controllers, programmable logic controllers (PLCs), and factory automation I/O cards frequently specify the EPF10K100EQC208-1X because it was qualified under IEC 61131 and various MIL-STD specifications in the late 1990s and 2000s, and these certifications remain valid for retrofit programs. The 2.5 V core, multi-voltage I/O (1.8 V to 5.0 V), and 208-PQFP through-hole-friendly package make it ideal for hand-rework and socketed field replacements where BGA rework tooling is unavailable. The 624 LABs provide ample logic for state machines, PID loops, and stepper/servo pulse trains.
Recommandé
Military and Aerospace Retrofit Boards
Defense and aerospace retrofit programs often target the EPF10K100EQC208-1X because of its long qualification history, MIL-STD-883 burn-in processing availability, and the relative ease of replacing through-hole PQFP packages in older systems. The device's 0.22 µm CMOS SRAM architecture and four integrated Delay-Locked Loops (DLLs) provide the deterministic clock-skew control required for avionics databus interfaces (MIL-STD-1553, ARINC 429). Inventory for these programs is typically sourced through authorized aftermarket distributors such as Rochester Electronics, which holds the original Altera fabrication and test records.
Recommandé
Medical Imaging Subsystem Glue Logic
In ultrasound and CT scanner subsystems, the EPF10K100EQC208-1X serves as the channel-count expansion glue logic between the analog front end (AFE), beamformer ASICs, and the host image-processing DSP. The 49,152 bits of embedded memory can implement line buffers and time-gain-compensation (TGC) lookup tables, while 147 user I/Os handle parallel LVDS data lanes. Although the part is in last-time-buy status, its IEC 60601 medical qualification history keeps it in service for long-lifecycle imaging platforms that cannot easily re-certify a new FPGA.
Recommandé
Test & Measurement Instrumentation Backplanes
Bench-top and ATE (Automated Test Equipment) instruments use the EPF10K100EQC208-1X to implement instrument-side protocol bridges, trigger generators, and timing sequencers. The 333.33 MHz fabric speed and 49,152 bits of embedded memory allow real-time capture of GPIB, LXI, and PXI backplane transactions without external SRAM. Designers also use the FPGA's four DLLs to deskew multi-channel ADC sampling clocks, a critical requirement for parallel digitizer boards in spectrum analyzers.
Recommandé
Legacy Industrial Display and Video Controllers
Older industrial flat-panel displays, video walls, and medical monitors used the EPF10K100EQC208-1X as a low-cost timing controller (TCON) replacement and as a bridge between LVDS/TTL display panels and the host graphics processor. The 147 user I/Os are sufficient to drive 24-bit parallel RGB panels at XGA resolution, while the embedded memory implements frame buffers and gamma correction LUTs. Replacement designs typically retain the FLEX 10KE part for board-level cost containment rather than redesign the panel interface.
Recommandé
Networking Line Card Bus Bridges
Enterprise and carrier-grade networking line cards built before 2010 often used the EPF10K100EQC208-1X to bridge between PHY chips, switch fabrics, and management processors running PowerPC or MIPS. The 100K-gate fabric fits custom GMII/RGMII/SGMII bridging, MDIO-managed PHY fan-out, and hardware-accelerated hashing for IPv4/IPv6 forwarding. Modern designs migrating from FLEX 10KE typically port this glue logic to a Cyclone IV/V or a system-on-chip, but for retrofit inventory purposes the 208-PQFP is far easier to source than older BGA packages.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour EPF10K100EQC208-1X — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | EPF10K100EQC208-1N | EPF10K100EQC208-1 |
|---|---|---|---|
| Package | 208-PQFP (28x28 mm) | 208-PQFP (28x28 mm) - same | 208-PQFP (28x28 mm) - same |
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Family | FLEX 10KE | FLEX 10KE | FLEX 10KE |
| Logic Cells | 4,992 | 4,992 | 4,992 |
| Logic Array Blocks (LABs) | 624 | 624 | 624 |
| User I/Os | 147 | 147 | 147 |
| Speed Grade | -1X (extended commercial corner) | -1N (standard commercial) | -1 (base commercial) |
| Embedded Memory | 49,152 bits | 49,152 bits | 49,152 bits |
| Core Voltage | 2.375 V to 2.625 V | 2.375 V to 2.625 V | 2.375 V to 2.625 V |
| Lifecycle Status | Last-time-buy / mature | Last-time-buy / mature | Last-time-buy / mature |
Principaux différenciateurs
- Extended commercial speed grade for tougher timing margins (vs EPF10K100EQC208-1N)
- Drop-in compatible with same 208-PQFP footprint (vs EPF10K100EQC208-1)
- Through-hole-friendly PQFP package for legacy rework (vs Cyclone IV EP4CE75F484 (BGA))
Notes de conception
Power sequencing is critical for FLEX 10KE: apply VCCINT (2.5 V) before any VCCIO rail (1.8/2.5/3.3/5.0 V) to avoid I/O latch-up that can permanently damage the device. Place a 100 µF bulk + 0.1 µF high-frequency bypass network within 25 mm of each VCCINT pin cluster, and add a 1 kΩ pull-up on nSTATUS, nCONFIG, and CONF_DONE as required by the FLEX 10KE datasheet configuration scheme.
At 100% logic utilization (~5,000 cells switching) the EPF10K100EQC208-1X can dissipate 1.5-2.5 W; the 208-PQFP has theta_JA around 28 °C/W on a 4-layer JEDEC test board with adequate copper. Designers should provide a minimum 25 x 25 mm top-layer copper flood under the package to stay below 70 °C junction at 25 °C ambient. Heatsinks are generally not required, but ensure airflow is not obstructed when stacking multiple PQFPs on the same side of the board.
Do not migrate a Quartus II 9.0 design to Quartus Prime 13.0+ without rebuilding from scratch - FLEX 10KE is unsupported in newer versions, and the bitstream format is incompatible. Ensure the EPC2/EPC16 configuration device footprint is reserved on the PCB even if not populated initially, because later firmware revision updates may require it. Finally, verify that VCCIO banks are not driven above 5.0 V, as the FLEX 10KE I/O ring tolerates up to 5.0 V only on specific bank configurations per datasheet pin tables.
Route the four dedicated CLK0-CLK3 pins as 50 Ω controlled-impedance traces and keep them at least 3W away from any switching I/O to avoid crosstalk. Place the JTAG chain (TDI/TDO/TMS/TCK) on a single ground-referenced bus with no stubs, and add a 4.7 kΩ pull-up on TCK to prevent spurious JTAG entry during power-up. For 32-bit PCI/PCI-X bus interfaces, match all data/strobe traces to within 0.5 mm to avoid bus-skew violations.
Informations de conformité
RoHS compliance and lead-free status confirmed via distributor listings (DigiKey, Mouser). AEC-Q100 not applicable - this is a programmable logic device, not an automotive analog/digital IC. Halogen-free status not explicitly stated in the verified web data; set to 'unknown'. Original Altera FLEX 10KE family was fabricated at 0.22 µm and qualified under various MIL-STD processing options for military customers (consult Rochester Electronics for MIL-STD-883 variants).
