FT232HL - Hi-Speed USB to UART/FIFO Bridge, LQFP-48 | FTDI
Référence : FT232HL ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $5.95 | $5,95 |
| 10 | $5.42 | $54,20 |
| 100 | $4.78 | $478,00 |
| 500 | $4.25 | $2 125,00 |
| 1 000 | $3.92 | $3 920,00 |
FT232HL Présentation
A USB-to-UART/FIFO bridge (or USB bridge IC) is a mixed-signal interface device that translates USB packet transactions on the host side into a parallel or serial peripheral stream on the device side. In the system hierarchy it sits between the USB host controller (an upstream function) and an embedded MCU, FPGA, or sensor (a downstream function). Bridges like the FT232HL eliminate the need for an on-board MCU to handle USB protocol, offloading PHY, framing, and enumeration onto a certified, driver-supported chip. Within the broader taxonomy the FT232HL is: USB bridge -> serial interface IC -> interface IC -> integrated circuit.
Key features include USB 2.0 Hi-Speed compliance (480 Mb/s), support for UART (up to 12 Mbaud), FIFO, FT1248, SPI host (up to 30 MHz via MPSSE) and I2C (up to 3.4 MHz) operating modes, an integrated 1.8V LDO, 3.3V I/O tolerance, and embedded 1024-byte EEPROM for VID/PID customization. The MPSSE (Multi-Protocol Synchronous Serial Engine) block lets the host drive SPI, I2C, and JTAG bit-bang streams directly from the USB endpoint, which is the FT232HL's signature use case.
Internally the FT232HL uses a 60 MHz internal reference and a hardened USB 2.0 PHY. The same die is offered in QFN-32 (FT232HQ), LQFP-48 (FT232HL), and LQFP-48 (FT232HL-TRAY/REEL). All variants share the same MPSSE performance and feature set; only the pinout, thermal pad, and pin count differ. The -L suffix on FT232H denotes the lead-free LQFP-48 package option.
Typical applications include USB-to-UART debug consoles, USB-to-SPI programmers for SPI flash and EEPROM, USB-to-I2C bridge boards, JTAG programming cables, and FPGA configuration loaders. Hobbyist and engineer-friendly boards like the Adafruit FT232H breakout and FTDI C232HM cable are built around this die. The wide driver support across Windows, macOS, and Linux (libFTDI, D2XX, VCP) reduces host-side integration effort.
A key design consideration is the 480 Mb/s USB 2.0 Hi-Speed signaling: route the D+/D- pair as a 90-ohm differential, keep them length-matched, and place the 27-ohm series termination close to the FT232HL pins. Provide a solid ground pour under the LQFP thermal pad and tie VBUS through a 10uF bulk plus 100nF decoupling cap. Reset state on power-up is selected by the default EEPROM image; verify VID/PID values before software bring-up.
Alternatives de remplacement direct pour FT232HL — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec FT232HL (même facteur de forme et même empreinte) — différant par Function, Mounting Type, Package, RoHS Status, Supply Voltage (VCC).
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
FT232HL-REEL
✅ Remplacement direct✓ En stock
$4.02 / unité
Voir la fiche technique →FT232HL-TRAY
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
FT232HQ
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
FT2232HL
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
CY7C65213-28SXIT
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
FT232HL Spécifications
| Fonction | USB 2.0 Hi-Speed to UART/FIFO/SPI/I2C bridge |
| USB Speed | Hi-Speed USB 2.0, 480 Mb/s |
| USB Compliance | USB 2.0 Hi-Speed |
| Serial Modes | UART, FIFO, FT1248, SPI host, I2C host (via MPSSE) |
| UART Data Rate | Up to 12 Mbaud |
| MPSSE Clock | Up to 30 MHz (SPI) |
| I2C Clock (MPSSE) | Up to 3.4 MHz |
| Number of Channels | 1 |
| Supply Voltage (VCC) | 3.0 V to 5.25 V (from VBUS or external 5V) |
| I/O Logic Level | 3.3 V (5 V tolerant inputs on most pins) |
| Internal LDO | 1.8 V core LDO integrated |
| EEPROM | Internal 1024-byte user-configurable |
| Boîtier | 48-LQFP (7x7 mm, lead-free) |
| Température de fonctionnement | -40 C to +85 C |
| Statut RoHS | Compliant (lead-free) |
| Type de montage | Surface Mount (LQFP) |
Configuration des broches de FT232HL
| Broche 1 | VBUS — USB VBUS sense input (5 V from host) |
| Broche 2 | VCC — 3.3 V LDO output / external 3.3 V supply |
| Broche 3 | VCCIO — I/O supply reference |
| Broche 4 | VPLL — 1.8 V PLL supply (filter cap) |
| Broche 5 | AGND — Analog ground |
| Broche 6 | XI — 12 MHz crystal input |
| Broche 7 | XO — 12 MHz crystal output |
| Broche 8 | RESET# — Active-low reset (tie to VCCIO via 10K) |
| Broche 9 | EECLK — EEPROM clock |
| Broche 10 | EEDATA — EEPROM data |
| Broche 11 | EECS — EEPROM chip select |
| Broche 12 | GND — Ground |
| Broche 13 | NC — Not connected (per datasheet) |
| Broche 14 | TEST — Test pin (tie to GND) |
| Broche 15 | OSCI — Oscillator input (NC for crystal) |
| Broche 16 | OSCO — Oscillator output (NC for crystal) |
| Broche 17 | D+ — USB D+ data line |
| Broche 18 | D- — USB D- data line |
| Broche 19 | VCC — USB PHY 3.3 V supply |
| Broche 20 | GND — Ground |
| Broche 21 | REFIN — Reference input |
| Broche 22 | REFOUT — Reference output (1.8 V) |
| Broche 23 | AD0 — MPSSE SCK / GPIO0 |
| Broche 24 | AD1 — MPSSE MOSI / GPIO1 |
| Broche 25 | AD2 — MPSSE MISO / GPIO2 |
| Broche 26 | AD3 — MPSSE CS / GPIO3 |
| Broche 27 | AD4 — MPSSE GPIO4 |
| Broche 28 | AD5 — MPSSE GPIO5 |
| Broche 29 | AD6 — MPSSE GPIO6 |
| Broche 30 | AD7 — MPSSE GPIO7 |
| Broche 31 | GND — Ground |
| Broche 32 | AC0 — MPSSE AC0 / I2C SCL |
| Broche 33 | AC1 — MPSSE AC1 / I2C SDA |
| Broche 34 | AC2 — MPSSE AC2 |
| Broche 35 | AC3 — MPSSE AC3 |
| Broche 36 | AC4 — MPSSE AC4 |
| Broche 37 | AC5 — MPSSE AC5 |
| Broche 38 | AC6 — MPSSE AC6 |
| Broche 39 | AC7 — MPSSE AC7 |
| Broche 40 | VCCIO — I/O supply reference |
| Broche 41 | GND — Ground |
| Broche 42 | PWREN# — Power enable (active low, signals VBUS present) |
| Broche 43 | SUSPEND — USB suspend state output |
| Broche 44 | TXD — UART transmit (async mode) |
| Broche 45 | RXD — UART receive (async mode) |
| Broche 46 | RTS# — UART request-to-send (async mode) |
| Broche 47 | CTS# — UART clear-to-send (async mode) |
| Broche 48 | VCC — USB PHY 3.3 V supply |
Applications typiques
FT232HL convient pour 7 applications: USB-to-UART Debug Bridge, USB-to-SPI Flash Programmer, USB-to-I2C Bridge Board, JTAG Programming Cable, FPGA Configuration Loader, USB Bit-Bang GPIO Expander, Industrial USB-Serial Isolated Module.
USB-to-UART Debug Bridge
The FT232HL's UART mode supports data rates up to 12 Mbaud with 3.3 V logic, making it an ideal USB-to-UART debug bridge for embedded MCUs and FPGAs. With USB 2.0 Hi-Speed (480 Mb/s) on the host side, it removes the bottleneck of Full-Speed UART bridges, while on the device side it exposes a true RS-232-style async stream with full hardware flow control. Connect VBUS at 5 V, route D+/D- as a 90-ohm differential, and bridge to a 4-wire UART header; the host sees a COM port via the FTDI VCP driver or a D2XX endpoint. This topology avoids needing an on-board MCU to handle USB protocol.
Recommandé
USB-to-SPI Flash Programmer
The FT232HL's MPSSE engine can drive SPI master mode at up to 30 MHz, which is more than sufficient for programming standard SPI flash (typically 50-104 MHz parts are clocked at 1/2 their max for programming). Use it in production test fixtures or field programmers where you want a pure USB-driven SPI master without an intermediate Cortex-M0. Typical circuit: FT232HL AD0=SCK, AD1=MOSI, AD2=MISO, AD3=CS, plus a 100K pull-up on CS. Throughput is limited by USB bulk endpoint framing (~1 MB/s effective), well within typical SPI flash write speeds.
Recommandé
USB-to-I2C Bridge Board
The FT232HL MPSSE block supports I2C master at up to 3.4 MHz (Fast-mode Plus compatible), enabling USB-to-I2C bridges for sensor hubs and EEPROM programmers. Use 2.2K external pull-ups on SDA/SCL, drive from AD0 (SCL) and AD1 (SDA), and use the libFTDI or D2XX MPSSE APIs on Windows/Linux/macOS. This removes the need for a dedicated USB-to-I2C bridge IC and reuses a single driver across UART/SPI/I2C designs.
Recommandé
JTAG Programming Cable
By driving the FT232HL MPSSE pins as TCK/TMS/TDI/TDO, the chip forms a low-cost USB-to-JTAG cable for CPLD/FPGA configuration and boundary-scan. The MPSSE clock (up to 30 MHz) comfortably exceeds JTAG TCK requirements of most modern FPGAs, while the FT232HL's 48-LQFP footprint fits in a thumb-drive-sized enclosure. OpenOCD and urjtag already support FT232HL-based JTAG cables, eliminating custom firmware.
Recommandé
FPGA Configuration Loader
The FT232HL's FIFO mode streams 8-bit parallel data into an FPGA's configuration port at sustained rates limited by the USB bulk pipeline (typically 1-2 MB/s). This is enough to load most small-to-medium FPGAs (e.g., Cyclone IV, Spartan-6) in under a second, making the FT232HL a strong low-cost choice for factory programming or field firmware updates. Connect AD0-AD7 to D0-D7 of the FPGA config port and use FTDI's D2XX drivers or libFTDI for streaming.
Recommandé
USB Bit-Bang GPIO Expander
When MPSSE is not in use, the FT232HL exposes up to 8 GPIO lines (AD0-AD7) plus 4 EEPROM-controlled GPIO lines, all driven directly from a USB endpoint via D2XX Bit-Bang mode. Engineers use this as a low-cost, OS-agnostic USB-GPIO for lab automation, LED driving, relay control, or production-line fixtures. Bit-bang mode toggles at up to 1 MHz per pin on the FT232HL's Hi-Speed pipe, well above the 1 kHz typical GPIO-update needs.
Recommandé
Industrial USB-Serial Isolated Module
Pair the FT232HL with a digital isolator (e.g., ADuM1411) and a bus-powered isolated DC-DC to build an industrial USB-to-RS-485/422 module. The FT232HL's 3.3 V I/O swings cleanly across the isolator barrier, and its robust driver support across Windows/Linux/macOS avoids custom host software. Add a MAX485 or ISL3179 on the isolated side to complete the link. This is a common industrial pattern where the FT232HL functions as the USB-side protocol engine.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour FT232HL — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | FT232HL-REEL | FT232HL-TRAY | FT232HQ | FT2232HL | CY7C65213-28SXIT |
|---|---|---|---|---|---|---|
| Brand | FTDI | FTDI | FTDI | FTDI | FTDI | Infineon |
| Package | 48-LQFP (7x7 mm) | 48-LQFP (7x7 mm) - same | 48-LQFP (7x7 mm) - same | 48-LQFP (7x7 mm) - same | 48-LQFP (7x7 mm) - same | 48-LQFP (7x7 mm) - same |
| USB Speed | Hi-Speed USB 2.0 (480 Mb/s) | Hi-Speed USB 2.0 (480 Mb/s) | Hi-Speed USB 2.0 (480 Mb/s) | Hi-Speed USB 2.0 (480 Mb/s) | Hi-Speed USB 2.0 (480 Mb/s) | Full-Speed USB (12 Mb/s) |
| Channels | 1 | 1 | 1 | 1 | 2 (dual) | 1 |
| MPSSE Engine | Yes (SPI/I2C/JTAG) | Yes | Yes | Yes | Yes (2x MPSSE) | No |
| UART Max Baud | 12 Mbaud | 12 Mbaud | 12 Mbaud | 12 Mbaud | 12 Mbaud | 1 Mbaud |
| FIFO Mode | Yes (8-bit parallel) | Yes | Yes | Yes | Yes | No |
| Internal EEPROM | 1024 bytes | 1024 bytes | 1024 bytes | 1024 bytes | 1024 bytes | Configurable via pins |
| Operating Temperature | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C |
| RoHS / Lead-Free | Yes (LQFP, lead-free) | Yes | Yes | Yes | Yes | Yes |
Principaux différenciateurs
- Single-channel Hi-Speed USB 2.0 with MPSSE (vs CY7C65213)
- Versatile multi-protocol serial engine (vs FT232RL)
- 48-LQFP footprint optimized for hand-rework (vs FT232HQ (QFN-32))
Notes de conception
Route the USB D+ and D- pair as a 90-ohm differential (USB 2.0 Hi-Speed characteristic impedance) with length matching to within 150 mil. Place the 27-ohm series termination resistors (or ferrite beads for EMI) within 5 mm of the FT232HL D+/D- pins. Keep the differential pair on the top layer with a continuous ground pour underneath; do not route over plane splits. Source: FTDI FT232H datasheet layout guidelines.
Decouple VCC (pin 2) and VCCIO (pins 3, 40) with 100 nF X7R ceramic capacitors placed within 2 mm of each pin, plus a single 10 uF bulk capacitor near the VBUS pin. The VPLL pin (4) requires its own 100 nF + 4.7 uF filter network (per FTDI reference design). Estimated: total bulk decoupling budget for a clean USB-2.0 enumeration is approximately 25 uF distributed across VCC, VCCIO, and VPLL.
Do not omit the external 12 MHz crystal on XI/XO (pins 6/7); the FT232HL cannot operate without a stable reference for its internal 480 MHz PLL. Use a crystal with 18-22 pF load capacitance and place within 5 mm of the IC. Common pitfall: leaving EECS (pin 11) floating when no EEPROM is used - this should be tied to GND so the FT232HL falls back to its internal default VID/PID rather than enumerating as an unknown device.
When driving an external target through MPSSE, place a 22-ohm series resistor on each AD0-AD7 and AC0-AC7 line if the cable to the target exceeds 50 mm. This damps ringing on the SPI/I2C edges and prevents double-clocking on long cables. Estimated: the MPSSE clock runs at up to 30 MHz, so a 50 mm unterminated trace presents roughly 5 nH of inductance which can cause >1 V overshoot on a 3.3 V edge.
Informations de conformité
Lead-free 48-LQFP package per FTDI product page. RoHS compliant. Not AEC-Q100 qualified; the FT232HL is intended for commercial/industrial USB bridge applications, not automotive.
