LTC2142IUP-14 - 14-Bit 65Msps Low-Power Dual ADC | ADI
Référence : LTC2142IUP-14 ✓ Actif| Qté | Prix unitaire | Total |
|---|---|---|
| 1 | $52.88 | $52,88 |
| 10 | $47.59 | $475,90 |
| 100 | $42.3 | $4 230,00 |
| 500 | $38.5 | $19 250,00 |
| 1 000 | $34.71 | $34 710,00 |
LTC2142IUP-14 Présentation
What is a dual simultaneous-sampling ADC? A dual ADC is a single integrated circuit containing two matched A/D converter channels that sample their analog inputs at the exact same instant, sharing a common clock. Within the broader signal chain hierarchy, the LTC2142IUP-14 sits inside the data-converter (ADC) class, which is itself a sub-category of data-acquisition ICs, mixed-signal semiconductors, and ultimately integrated circuits. Each converter is preceded by an input track-and-hold and feeds a common reference, allowing direct-IF sampling and quadrature demodulation in communications receivers.
Key headline parameters include 14-bit resolution, 65 Msps conversion rate per channel, 73.1 dB SNR, 90 dB SFDR, and a low 100 mW per-channel power dissipation. The device accepts single-ended or differential analog inputs with an input range of 1 Vp-p to 2 Vp-p (set by the MODE pin) and operates from a single 1.8 V analog supply. Digital outputs are LVDS-compatible, easing routing to an FPGA or ASIC across a noisy PCB. A flexible parallel or serial programming interface configures output format, gain, and test patterns.
Architecturally, the converter uses a multi-stage pipelined core with proprietary linearization techniques that preserve linearity at high input frequencies, with a typical -3 dB analog input bandwidth of 125 MHz that comfortably exceeds the 65 Msps Nyquist requirement. This makes the part well suited to undersampling intermediate-frequency (IF) signals in wireless infrastructure.
Typical applications include 3G/4G cellular base-station receivers, communications imaging, portable instrumentation, ultrasound scanners, and multi-channel data-acquisition cards where channel-to-channel phase coherence is mandatory. Designers frequently pair the LTC2142IUP-14 with low-noise LDOs such as the LT1761 and clock-distribution ICs from the AD951x family.
When laying out the PCB, place the analog inputs as close to the ADC pins as possible, use a solid ground plane under the package, and route LVDS outputs with controlled 100 ohm differential impedance. The exposed paddle (EP) must be soldered to a low-impedance ground pad to provide both the electrical ground return and the primary thermal path for the 100 mW internal dissipation.
This page synthesizes distributor pricing, package-faithful drop-in alternatives, and applied design notes that go beyond the manufacturer datasheet. It is intended as an engineering-grade reference for BOM managers and hardware designers evaluating the LTC2142IUP-14 for new designs or service replacements.
Alternatives de remplacement direct pour LTC2142IUP-14 — même boîtier, compatible broche à broche. Les références à boîtier différent nécessitant une retouche du PCB sont exclues.
Variantes de cette série
Modèles de la même série directement compatibles avec LTC2142IUP-14 (même facteur de forme et même empreinte) — différant par Package, Sample Rate, Resolution, Input Type, SNR.
Outil de comparaison rapide — sélectionnez des références alternatives pour une comparaison côte à côte :
LTC2142CUP-14#PBF
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
LTC2141IUP-14#PBF
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
LTC2140IUP-14#PBF
✅ Remplacement direct ⚠️ Spécifications non vérifiées📋 Alternative de référence (hors catalogue)
AD9251BCPZ-40
✅ Remplacement direct📋 Alternative de référence (hors catalogue)
LTC2142IUP-14 Valeurs maximales et caractéristiques électriques
| Résolution | 14 bit |
| Number of Channels | 2 (simultaneous sampling) |
| Sample Rate | 65 Msps per channel |
| Architecture | Pipelined |
| SNR | 73.1 dB |
| SFDR | 90 dB |
| Input Range | 1 Vp-p to 2 Vp-p (MODE configurable) |
| Analog Input Bandwidth | 125 MHz (typ) |
| Analog Supply Voltage | 1.8 V |
| Digital Output Interface | LVDS (parallel) |
| Power Dissipation | 100 mW per channel (typ) |
| Plage de température de fonctionnement | -40C to +85C (industrial) |
| Boîtier | 64-QFN (UP) 9x9 mm with exposed pad |
| Configuration Interface | Parallel or Serial (SPI-compatible) |
| Pin/Package Count | 64 pins |
| Type de montage | Surface Mount |
| Statut RoHS | Compliant (PBF suffix) |
Configuration des broches de LTC2142IUP-14
| Broche 1 | INA+ — Channel A positive analog input |
| Broche 2 | INA- — Channel A negative analog input |
| Broche 3 | VCM_A — Channel A common-mode voltage |
| Broche 4 | SENSE_A — Channel A input range select |
| Broche 5 | REFT_A — Channel A reference top decoupling |
| Broche 6 | REFB_A — Channel A reference bottom decoupling |
| Broche 7 | GND — Ground |
| Broche 8 | VDD_A — 1.8 V analog supply (channel A) |
| Broche 9 | OGND_A — Output driver ground (channel A) |
| Broche 10 | OVDD_A — Output driver supply (channel A) |
| Broche 11 | D0A_N — Channel A LVDS data bit 0 (negative) |
| Broche 12 | D0A_P — Channel A LVDS data bit 0 (positive) |
| Broche 13 | D1A_N — Channel A LVDS data bit 1 (negative) |
| Broche 14 | D1A_P — Channel A LVDS data bit 1 (positive) |
| Broche 15 | D2A_N — Channel A LVDS data bit 2 (negative) |
| Broche 16 | D2A_P — Channel A LVDS data bit 2 (positive) |
| Broche 17 | D3A_N — Channel A LVDS data bit 3 (negative) |
| Broche 18 | D3A_P — Channel A LVDS data bit 3 (positive) |
| Broche 19 | D4A_N — Channel A LVDS data bit 4 (negative) |
| Broche 20 | D4A_P — Channel A LVDS data bit 4 (positive) |
| Broche 21 | D5A_N — Channel A LVDS data bit 5 (negative) |
| Broche 22 | D5A_P — Channel A LVDS data bit 5 (positive) |
| Broche 23 | D6A_N — Channel A LVDS data bit 6 (negative) |
| Broche 24 | D6A_P — Channel A LVDS data bit 6 (positive) |
| Broche 25 | D7A_N — Channel A LVDS data bit 7 (negative) |
| Broche 26 | D7A_P — Channel A LVDS data bit 7 (positive) |
| Broche 27 | D8A_N — Channel A LVDS data bit 8 (negative) |
| Broche 28 | D8A_P — Channel A LVDS data bit 8 (positive) |
| Broche 29 | D9A_N — Channel A LVDS data bit 9 (negative) |
| Broche 30 | D9A_P — Channel A LVDS data bit 9 (positive) |
| Broche 31 | D10A_N — Channel A LVDS data bit 10 (negative) |
| Broche 32 | D10A_P — Channel A LVDS data bit 10 (positive) |
| Broche 33 | D11A_N — Channel A LVDS data bit 11 (negative) |
| Broche 34 | D11A_P — Channel A LVDS data bit 11 (positive) |
| Broche 35 | D12A_N — Channel A LVDS data bit 12 (negative) |
| Broche 36 | D12A_P — Channel A LVDS data bit 12 (positive) |
| Broche 37 | D13A_N — Channel A LVDS data bit 13 (negative) |
| Broche 38 | D13A_P — Channel A LVDS data bit 13 (positive) |
| Broche 39 | CLKOUTA_N — Channel A LVDS clock output (negative) |
| Broche 40 | CLKOUTA_P — Channel A LVDS clock output (positive) |
| Broche 41 | FRAMA_N — Channel A LVDS frame output (negative) |
| Broche 42 | FRAMA_P — Channel A LVDS frame output (positive) |
| Broche 43 | OVDD_B — Output driver supply (channel B) |
| Broche 44 | OGND_B — Output driver ground (channel B) |
| Broche 45 | VDD_B — 1.8 V analog supply (channel B) |
| Broche 46 | GND — Ground |
| Broche 47 | REFB_B — Channel B reference bottom decoupling |
| Broche 48 | REFT_B — Channel B reference top decoupling |
| Broche 49 | SENSE_B — Channel B input range select |
| Broche 50 | VCM_B — Channel B common-mode voltage |
| Broche 51 | INB- — Channel B negative analog input |
| Broche 52 | INB+ — Channel B positive analog input |
| Broche 53 | REFP — Positive reference decoupling |
| Broche 54 | REFN — Negative reference decoupling |
| Broche 55 | REFH — Reference high |
| Broche 56 | REFL — Reference low |
| Broche 57 | MODE — Mode pin (input range / output format) |
| Broche 58 | OGND — Output ground |
| Broche 59 | OVDD — Output supply |
| Broche 60 | SDO — Serial data output (configuration interface) |
| Broche 61 | SDI — Serial data input (configuration interface) |
| Broche 62 | SCK — Serial configuration clock |
| Broche 63 | CS — Serial chip select / parallel config mode |
| Broche 64 | CLK+ — Sampling clock positive input |
| Broche EP | EP — Exposed thermal pad - must be soldered to ground pad for electrical ground and thermal dissipation |
Applications typiques
LTC2142IUP-14 convient pour 6 applications: Cellular Base-Station Receiver IF Digitization, Portable Ultrasonic Imaging Systems, Communications / Software-Defined Radio (SDR), Multi-Channel Data Acquisition Cards, Phased-Array Radar and Beamforming Receivers, Portable Instrumentation and Test Equipment.
Cellular Base-Station Receiver IF Digitization
The LTC2142IUP-14's simultaneous dual-channel sampling makes it a natural fit for cellular base-station receivers that must digitize I and Q baseband or IF signals at the same instant. Its 73.1 dB SNR and 90 dB SFDR at 65 Msps comfortably exceed the dynamic-range requirements for UMTS/LTE multi-carrier signals, while the 125 MHz analog input bandwidth permits direct IF sampling at 30 to 70 MHz, eliminating an analog downconversion stage. Placed after the SAW filter and LNA chain, the two ADC cores feed the LVDS outputs directly to an FPGA where digital downconversion and channelization occur. Compared with switching to a single-channel ADC, the matched dual cores guarantee zero aperture-skew between I and Q paths, preserving EVM under load.
Recommandé
Portable Ultrasonic Imaging Systems
Medical and industrial ultrasonic imaging arrays require multiple receiver channels that sample returned echoes at the same instant to compute beamformed images. The LTC2142IUP-14's dual simultaneous-sampling 14-bit cores, 100 mW per-channel power dissipation, and small 9x9 mm QFN footprint let designers pack dense multi-channel receiver boards into a portable cart or handheld probe. With 73 dB SNR, the part resolves the >40 dB dynamic range needed to image both strong specular echoes and weak scatter echoes from tissue or weld defects. Power dissipation of 200 mW per dual ADC keeps thermal rise modest in a sealed enclosure, and the LVDS outputs route cleanly to an FPGA beamformer over a backplane.
Recommandé
Communications / Software-Defined Radio (SDR)
Software-defined-radio platforms demand wideband ADC front-ends that capture large RF/IF slices for downstream DSP. The LTC2142IUP-14's 125 MHz analog input bandwidth and 65 Msps sample rate let an SDR designer alias-band sample a 0-30 MHz spectrum while still meeting Nyquist for many narrowband waveforms. The dual-channel architecture supports direct-conversion I/Q digitization, replacing a pair of matched single-channel ADCs and removing the need for manual gain/offset calibration between channels. At 100 mW per channel, the part fits thermally inside fanless SDR enclosures. The exposed-paddle QFN package allows direct soldering to an inner ground plane, which is essential for the 90 dB SFDR performance at high input frequencies.
Recommandé
Multi-Channel Data Acquisition Cards
PCIe and PXIe data-acquisition cards for industrial test, vibration analysis, and phased-array sonar use the LTC2142IUP-14 to digitize 8, 16, or more channels by ganging multiple dual ADCs across a backplane. Simultaneous sampling across all channels is mandatory for time-coherent vibration, modal analysis, or sonar beamforming - a problem the matched dual cores solve inherently. The LVDS outputs are routed as 100 ohm differential pairs to an FPGA that performs channel synchronization, decimation, and DMA transfer to the host. The 64-QFN 9x9 mm footprint keeps each dual-ADC land pattern compact, allowing 4 to 8 dual-ADCs (8 to 16 channels) on a single acquisition card without violating routing density limits.
Recommandé
Phased-Array Radar and Beamforming Receivers
Phased-array radar receivers depend on dozens to hundreds of synchronized receive channels; a small error in sample timing across the array can defocus the beam. The LTC2142IUP-14's two matched cores sharing one clock pin and one reference allow designers to cascade dual ADCs with predictable aperture delay, simplifying beamformer calibration. With 73 dB SNR and 90 dB SFDR, the part digitizes the wide dynamic range typical of radar returns from large and small targets. The 1.8 V supply aligns with modern low-power FPGA and DSP rails, simplifying power tree design. For 16+ element arrays, multiple LTC2142IUP-14s are clocked from a single low-jitter AD951x distribution IC to maintain sub-picosecond inter-channel skew.
Recommandé
Portable Instrumentation and Test Equipment
Handheld oscilloscopes, spectrum analyzers, and protocol analyzers benefit from the LTC2142IUP-14's dual-channel simultaneous sampling at 65 Msps - enough bandwidth to analyze audio, vibration, and low-speed serial buses while remaining battery-friendly at 200 mW total power. The 64-QFN footprint permits dense two-channel front-ends in a slim probe body or instrument chassis. The 1.8 V analog and digital supplies integrate with Li-ion battery PMIC outputs through a low-dropout regulator. The 14-bit resolution is sufficient for 0.5 percent-accurate measurements on test signals in the 1-10 MHz range commonly found in embedded and industrial debug scenarios.
Recommandé
Récapitulatif des produits recommandés
Données de référence d'ingénierie pour LTC2142IUP-14 — comparaison, recommandations de conception et informations de conformité.
Guide de sélection
Comparaison avec les alternatives
| Paramètre | Ce produit | LTC2142CUP-14#PBF | LTC2141IUP-14#PBF | LTC2140IUP-14#PBF | AD9251BCPZ-40 |
|---|---|---|---|---|---|
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Package | 64-QFN (UP) 9x9 mm | 64-QFN (UP) 9x9 mm - same | 64-QFN (UP) 9x9 mm - same | 64-QFN (UP) 9x9 mm - same | 64-LFCSP (9x9) - footprint compatible |
| Resolution | 14 bit | 14 bit | 14 bit | 14 bit | 14 bit |
| Sample Rate | 65 Msps | 65 Msps | 40 Msps | 25 Msps | 40 Msps |
| Number of Channels | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 1 |
| SNR | 73.1 dB | 73.1 dB | 73.1 dB | 73.1 dB | 72 dB (typ) |
| Power Dissipation | 100 mW/ch | 100 mW/ch | 85 mW/ch (lower speed) | 70 mW/ch (lower speed) | 60 mW/ch (single channel) |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial) | -40C to +85C (industrial) | -40C to +85C (industrial) | -40C to +85C (industrial) |
Principaux différenciateurs
- Dual simultaneous-sampling 14-bit cores in a single 9x9 mm QFN (vs AD9251BCPZ-40)
- Higher sample rate than the LTC2140IUP-14 family sibling (vs LTC2140IUP-14#PBF)
- Lower power dissipation than the LTC2174IUKG-14 (higher-speed sibling) (vs LTC2174IUKG-14)
Notes de conception
Route the analog input traces (INA+/INA-, INB+/INB-) as a 100 ohm differential pair with controlled impedance, using a solid ground reference plane on the layer immediately below. Keep trace length below 25 mm to preserve the 125 MHz input bandwidth and minimize common-mode pickup. Place the input RC anti-alias filter within 5 mm of the ADC input pins and use C0G/NP0 capacitors for best linearity.
Estimated: with 200 mW total dissipation in the 9x9 mm QFN package, the junction-to-ambient thermal resistance is approximately 28 C/W on a 4-layer JEDEC test board. The exposed paddle (EP) is the primary thermal path; design the PCB land pattern with at least 16 thermal vias (0.3 mm drill, 0.5 mm pitch) stitching EP to the inner ground plane. For applications above 70C ambient, add a copper pour on the top layer to spread heat from the EP.
Provide separate analog (VDD_A, VDD_B) and digital (OVDD_A, OVDD_B) supply rails, each decoupled with a 10 uF bulk + 0.1 uF high-frequency cap placed within 3 mm of each supply pin. Drive the 1.8 V analog rail from a low-noise LDO such as the LT3042 or LT1761; avoid tying the analog and digital returns together - use a star-ground connection at the EP pad. Keep clock and LVDS output traces away from the analog input traces to prevent digital noise coupling.
The LVDS outputs must be terminated with a 100 ohm differential resistor placed close to the receiving FPGA. Route LVDS pairs as tightly-coupled 100 ohm differential traces over a continuous ground plane; keep intra-pair skew below 10 ps and inter-pair skew below 50 ps. If the receiving FPGA lacks built-in LVDS termination, add external 100 ohm resistors across each LVDS pair at the FPGA pin.
Do not float the SENSE pin - tie it to GND for 1 Vp-p input range or to VDD for 2 Vp-p input range. Floating SENSE leaves the input range undefined and degrades SNR. The MODE pin also configures LVDS output format; verify the FPGA is configured to match. Finally, always enable the part via the serial interface after power-up; the default power-on state holds outputs in high-impedance.
Informations de conformité
RoHS compliant per the #PBF suffix ordering code. AEC-Q100 is not applicable for this commercial/industrial dual ADC. Halogen-free status not stated in the verified data; marked as unknown.
