5CSEBA5U19I7N vs 5CSEBA6U19I7N तुलना
विस्तृत दोनों ओर की तुलना 5CSEBA5U19I7N द्वारा Intel और 5CSEBA6U19I7N द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Intel
5CSEBA5U19I7N - Cyclone V SE SoC FPGA 85K LE Dual ARM Cortex-A9 | Intel
5CSEBA5U19I7N ✓ सक्रियIntel
5CSEBA6U19I7N - Cyclone V SE SoC FPGA, 110K LE, Dual ARM Cortex-A9 800MHz | Intel
5CSEBA6U19I7N ✓ सक्रियविशेषता तुलना
| पैरामीटर | 5CSEBA5U19I7N | 5CSEBA6U19I7N |
|---|---|---|
| ब्रांड | Intel | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | सक्रिय | सक्रिय |
| Product Type | SoC FPGA (System-on-Chip FPGA) | — |
| Series | Cyclone V SE | 5CSEBA6 |
| Logic Elements | 85,000 | 110,000 |
| Hard Processor System | Dual ARM Cortex-A9 MPCore with CoreSight | Dual-core ARM Cortex-A9 MPCore |
| Core Frequency | 800 MHz (typical), up to 925 MHz | — |
| Process Technology | 28 nm TSMC low-power | TSMC 28 nm low-power |
| पैकेज | 484-pin UBG (UFBGA) 19x19 mm | 484-pin UBGAFBGA (UBGA-484, 19x19 mm) |
| सप्लाई वोल्टेज | 1.1 V core | Multi-rail (1.1 V core, 1.5/1.8/2.5/3.0/3.3 V I/O) |
| FPGA User I/O | 66 (per datasheet front-page snippet) | — |
| Embedded Memory | Approximately 4,450 Kbits | 4.45 Mbits (M10K + MLAB) |
| DSP Blocks | 87 variable-precision (18x18 multipliers) | 112 (18x18 multipliers) |
| Transceivers | Up to 5 Gbps (Cyclone V SE feature) | Up to 9 channels, 3.125 Gbps |
| HPS Peripherals | USB 2.0 OTG, EMAC, CAN, SPI, I2C, UART, SD/MMC, NAND | — |
| ऑपरेटिंग तापमान | -40C to +100C (Industrial grade, suffix I) | -40C to +100C (Industrial) |
| माउंटिंग प्रकार | Surface Mount (BGA) | Surface Mount (BGA) |
| MSL स्तर | [DATA_NEEDED: MSL level] | — |
| RoHS स्थिति | Compliant (per Heisener listing and product family) | Compliant |
| Family | — | Cyclone V SE SoC FPGA |
| Device Variant | — | 5CSEA6 (U19 package, 110K LE) |
| HPS Maximum Frequency | — | 800 MHz |
| Hard Memory Controller | — | DDR3, DDR3L, LPDDR2 |
| PLLs | — | 6 (FPGA) + 3 (HPS) |
| User I/O Banks | — | 8 |
| Maximum User I/O | — | 288 (package-dependent) |
| Configuration Modes | — | JTAG, Active Serial (AS), Passive Serial (PS), Fast Passive Parallel (FPP) |