CDK1307DILP40 vs CDK1308AILP40 तुलना
विस्तृत दोनों ओर की तुलना CDK1307DILP40 द्वारा MaxLinear और CDK1308AILP40 द्वारा MaxLinear. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | CDK1307DILP40 | CDK1308AILP40 |
|---|---|---|
| ब्रांड | MaxLinear | MaxLinear |
| श्रेणी | ADC/DAC | ADC/DAC |
| लाइफसाइकिल स्थिति | सक्रिय | सक्रिय |
| रेज़ोल्यूशन | 13 bit | 10 bit |
| Sampling Rate (max) | 80 MSPS | — |
| Power Dissipation (typ) | 60 mW at 80 MSPS | — |
| Family Power Grades | 17 / 19 / 33 / 50 / 60 / 75 mW across speed grades | — |
| SNR | 72.4 dB at Fin = 8 MHz | — |
| Analog Supply Voltage | 1.8 V (core) | — |
| I/O Supply Voltage | 1.7 V to 3.6 V | — |
| Output Interface | Parallel CMOS | — |
| Reference | Internal reference circuitry | Internal (no external reference required) |
| Clock Input | Differential, low-jitter | — |
| Track-and-Hold | Highly linear, optimized to Nyquist | — |
| Idle Modes | Standby and Power Down | — |
| पैकेज | 40-pin QFN | 40-pin QFN |
| Pin Compatibility | Pin-compatible with CDK1308 | — |
| Pin Compatibility (family) | Same 40-pin QFN for A/B/C/D speed grades | — |
| Maximum Sample Rate | — | 20 MSPS |
| Family Sample Rate Options | — | 20 / 40 / 65 / 80 MSPS |
| Architecture | — | Proprietary, digital error correction |
| Digital Interface | — | CMOS, parallel |
| Control Interface | — | CMOS |
| Power-Down Pin (PD_N) | — | Yes (active low) |
| Sleep Pin (SLP_N) | — | Yes (active low) |
| माउंटिंग प्रकार | — | Surface Mount |
| Power Consumption | — | Ultra-low (per family datasheet, exact value [DATA_NEEDED: power consumption mW]) |
| ऑपरेटिंग तापमान रेंज | — | [DATA_NEEDED: operating temperature range] |
| सप्लाई वोल्टेज | — | [DATA_NEEDED: AVDD / DRVDD values] |
| RoHS स्थिति | — | Compliant (per distributor listings) |
| Manufacturer | — | MaxLinear (formerly Exar Corporation) |