CDK1307DILP40 vs CDK1308AILP40 比較
詳細な並列比較: CDK1307DILP40 メーカー: MaxLinear および CDK1308AILP40 メーカー: MaxLinear。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | CDK1307DILP40 | CDK1308AILP40 |
|---|---|---|
| ブランド | MaxLinear | MaxLinear |
| カテゴリ | ADC/DAC | ADC/DAC |
| ライフサイクル状態 | 有効 | 有効 |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $9.60 | $4.10 |
| 分解能 | 13 bit | 10 bit |
| Sampling Rate (max) | 80 MSPS | — |
| Power Dissipation (typ) | 60 mW at 80 MSPS | — |
| Family Power Grades | 17 / 19 / 33 / 50 / 60 / 75 mW across speed grades | — |
| SNR | 72.4 dB at Fin = 8 MHz | — |
| Analog Supply Voltage | 1.8 V (core) | — |
| I/O Supply Voltage | 1.7 V to 3.6 V | — |
| Output Interface | Parallel CMOS | — |
| Reference | Internal reference circuitry | Internal (no external reference required) |
| Clock Input | Differential, low-jitter | — |
| Track-and-Hold | Highly linear, optimized to Nyquist | — |
| Idle Modes | Standby and Power Down | — |
| パッケージ | 40-pin QFN | 40-pin QFN |
| Pin Compatibility | Pin-compatible with CDK1308 | — |
| Pin Compatibility (family) | Same 40-pin QFN for A/B/C/D speed grades | — |
| Maximum Sample Rate | — | 20 MSPS |
| Family Sample Rate Options | — | 20 / 40 / 65 / 80 MSPS |
| Architecture | — | Proprietary, digital error correction |
| Digital Interface | — | CMOS, parallel |
| Control Interface | — | CMOS |
| Power-Down Pin (PD_N) | — | Yes (active low) |
| Sleep Pin (SLP_N) | — | Yes (active low) |
| 実装タイプ | — | Surface Mount |
| Power Consumption | — | Ultra-low (per family datasheet, exact value [DATA_NEEDED: power consumption mW]) |
| 動作温度範囲 | — | [DATA_NEEDED: operating temperature range] |
| 電源電圧 | — | [DATA_NEEDED: AVDD / DRVDD values] |
| RoHS ステータス | — | Compliant (per distributor listings) |
| Manufacturer | — | MaxLinear (formerly Exar Corporation) |