CDK1307DILP40 vs CDK1308AILP40 비교
다음의 상세 나란히 비교: CDK1307DILP40 제조: MaxLinear 및 CDK1308AILP40 제조: MaxLinear. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | CDK1307DILP40 | CDK1308AILP40 |
|---|---|---|
| 브랜드 | MaxLinear | MaxLinear |
| 카테고리 | ADC/DAC | ADC/DAC |
| 수명 주기 상태 | 활성 | 활성 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.60 | $4.10 |
| 분해능 | 13 bit | 10 bit |
| Sampling Rate (max) | 80 MSPS | — |
| Power Dissipation (typ) | 60 mW at 80 MSPS | — |
| Family Power Grades | 17 / 19 / 33 / 50 / 60 / 75 mW across speed grades | — |
| SNR | 72.4 dB at Fin = 8 MHz | — |
| Analog Supply Voltage | 1.8 V (core) | — |
| I/O Supply Voltage | 1.7 V to 3.6 V | — |
| Output Interface | Parallel CMOS | — |
| Reference | Internal reference circuitry | Internal (no external reference required) |
| Clock Input | Differential, low-jitter | — |
| Track-and-Hold | Highly linear, optimized to Nyquist | — |
| Idle Modes | Standby and Power Down | — |
| 패키지 | 40-pin QFN | 40-pin QFN |
| Pin Compatibility | Pin-compatible with CDK1308 | — |
| Pin Compatibility (family) | Same 40-pin QFN for A/B/C/D speed grades | — |
| Maximum Sample Rate | — | 20 MSPS |
| Family Sample Rate Options | — | 20 / 40 / 65 / 80 MSPS |
| Architecture | — | Proprietary, digital error correction |
| Digital Interface | — | CMOS, parallel |
| Control Interface | — | CMOS |
| Power-Down Pin (PD_N) | — | Yes (active low) |
| Sleep Pin (SLP_N) | — | Yes (active low) |
| 실장 유형 | — | Surface Mount |
| Power Consumption | — | Ultra-low (per family datasheet, exact value [DATA_NEEDED: power consumption mW]) |
| 동작 온도 범위 | — | [DATA_NEEDED: operating temperature range] |
| 공급 전압 | — | [DATA_NEEDED: AVDD / DRVDD values] |
| RoHS 상태 | — | Compliant (per distributor listings) |
| Manufacturer | — | MaxLinear (formerly Exar Corporation) |